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PRELIMINARY DATA SHEET
MICRONAS
MSP 44x8G Multistandard Sound Processor
Edition Feb. 25, 2000 6251-516-1PD
MICRONAS
MSP 44x8G
Contents Page 5 6 6 7 8 8 9 9 9 9 10 10 12 12 12 12 12 13 13 13 13 13 13 13 13 14 14 14 14 15 15 15 16 16 17 17 17 17 17 17 17 17 20 21 21 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.3. 2.4. 2.4.1. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.6. 2.6.1. 2.6.2. 2.7. 2.7.1. 2.7.2. 2.8. 2.9. 2.10. 2.11. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.4.1. 3.1.4.2. 3.1.4.3. 3.1.4.4. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. Title Introduction Features of the MSP 44x8G Family MSP 44x8G Version List MSP 44x8G Versions and their Application Fields Functional Description Architecture of the MSP 44x8G Family MSP 44x8G Sound IF Processing Analog Sound IF Input Demodulator: Standards and Features Preprocessing of Demodulator Signals Automatic Sound Select Manual Mode Preprocessing for SCART and I2S Input Signals Source Selection and Output Channel Matrix Mixing Unit Audio Baseband Processing Automatic Volume Correction (AVC) Main and Aux Outputs Quasi-Peak Detector SCART Signal Routing SCART DSP In and SCART Out Select Stand-by Mode I2S Bus Interfaces Synchronous I2S-Interface(s) Asynchronous I2S-Interface ADR Bus Interface Digital Control I/O Pins and Status Change Indication Preemphasis Clock PLL Oscillator and Crystal Specifications Control Interface I2C Bus Interface Device and Subaddresses Description of CONTROL Register Protocol Description Proposals for General MSP 44x8G I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C Controlling MSP 44x8G Programming Interface User Registers Overview Description of User Registers STANDARD SELECT Register STANDARD RESULT Register
PRELIMINARY DATA SHEET
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PRELIMINARY DATA SHEET
MSP 44x8G
Contents, continued Page 22 25 26 33 34 34 34 34 34 35 35 35 37 37 39 42 45 48 50 50 51 51 51 52 53 54 54 55 56 57 58 60 62 62 63 66 69 69 70 71 71 72 72 Section 3.3.2.3. 3.3.2.4. 3.3.2.5. 3.3.2.6. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5. 3.5.6. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.2.4. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 4.6.3.9. 4.6.3.10. 5. 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. Title Write Registers on I2C Subaddress 10hex Read Registers on I2C Subaddress 11hex Write Registers on I2C Subaddress 12hex Read Registers on I2C Subaddress 13hex Programming Tips Examples of Minimum Initialization Codes B/G-FM (A2 or NICAM) BTSC-Stereo BTSC-SAP with SAP at Main Channel FM-Stereo Radio Automatic Standard Detection Software Flow for Interrupt driven STATUS Check Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions (TA = 0 to 70 C) General Recommended Operating Conditions Analog Input and Output Recommendations Recommendations for Analog Sound IF Input Signal Crystal Recommendations Characteristics General Characteristics Digital Inputs, Digital Outputs Reset Input and Power-Up I2C-Bus Characteristics I2S-Bus Characteristics Analog Baseband Inputs and Outputs, AGNDC Sound IF Inputs Power Supply Rejection Analog Performance Sound Standard Dependent Characteristics Appendix A: Overview of TV-Sound Standards NICAM 728 A2-Systems BTSC-Sound System Japanese FM Stereo System (EIA-J) FM Satellite Sound FM-Stereo Radio
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Contents, continued Page 73 73 74 74 74 74 75 76 76 77 77 78 78 78 78 79 79 79 79 79 79 80 80 80 80 80 80 82 82 82 83 84 Section 6. 6.1. 6.2. 6.3. 6.3.1. 6.3.1.1. 6.3.1.2. 6.3.2. 6.3.3. 6.3.4. 6.4. 6.4.1. 6.4.2. 6.4.3. 6.4.4. 6.5. 6.5.1. 6.5.2. 6.5.3. 6.5.4. 6.5.5. 6.6. 6.6.1. 6.6.2. 6.7. 6.7.1. 6.7.2. 7. 7.1. 7.2. 7.3. 8. Title Appendix B: Manual Mode Demodulator Write and Read Registers for Manual Mode DSP Write and Read Registers for Manual Mode Manual Mode: Description of Demodulator Write Registers Automatic Switching between NICAM and Analog Sound Function in Automatic Sound Select Mode Function in Manual Mode A2 Threshold Carrier-Mute Threshold DCO-Registers Manual Mode: Description of Demodulator Read Registers NICAM Mode Control/Additional Data Bits Register Additional Data Bits Register CIB Bits Register NICAM Error Rate Register Manual Mode: Description of DSP Write Registers Additional Channel Matrix Modes FM Fixed Deemphasis FM Adaptive Deemphasis NICAM Deemphasis Identification Mode for A2 Stereo Systems Manual Mode: Description of DSP Read Registers Stereo Detection Register for A2 Stereo Systems DC Level Register Demodulator Source Channels in Manual Mode Terrestrial Sound Standards SAT Sound Standards Appendix C: Application Information Exclusions of Audio Baseband Features Phase Relationship of Analog Outputs Application Circuit Data Sheet History
PRELIMINARY DATA SHEET
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PRELIMINARY DATA SHEET
MSP 44x8G
This generation of TV sound processing ICs includes versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. The MSP 44x8G versions are pin and software compatible to other MSP families. Standard selection requires only a single I2C transmission. The MSP 44x8G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/ stereo/bilingual; no I2C interaction is necessary (Automatic Sound Selection). The ICs are produced in submicron CMOS technology and are available in the following packages: PQFP80, PLQFP64, and PSDIP64.
Multistandard Sound Processor Family
1. Introduction The MSP 44x8G family of Multistandard Sound Processors covers the sound processing of all analog TVStandards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Fig. 1-1 shows a simplified functional block diagram of the MSP 44x8G. The high-quality A/D and D/A converters offer the full audio bandwidth of 20 kHz and the backend DSP processing is performed at a 48 kHz sample rate. The MSP 44x8G has been designed for the usage in hybrid set-top boxes and multimedia applications. Its asynchronous I2S slave interface allows the reception of digital stereo signals with arbitrary sample rates ranging from 5 to 50 kHz. Synchronization is performed by means of an adaptive sample rate converter.
Sound IF1 ADC Sound IF2 I2S1 I2S2 I2S3 SCART1 SCART2 SCART3 SCART4 MONO SCART DSP Input Select
Demodulator
Preprocessing
Main Sound Processing
DAC
Main Channel
Source Select
synchron. I2 S asychron. I2 S
Prescale
Aux Sound Processing
DAC
Aux Channel I2S
DAC SCART1 ADC Prescale DAC SCART Output Select SCART2
Fig. 1-1: Simplified functional block diagram of the MSP 44x8G
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MSP 44x8G
1.1. Features of the MSP 44x8G Family
Feature Standard Selection with single I2C transmission Automatic Standard Detection of terrestrial TV standards Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS Two selectable sound IF (SIF) inputs Automatic Carrier Mute function Interrupt output programmable (indicating status change) Main/Aux channel with volume, balance, bass, treble, loudness AVC: Automatic Volume Correction Two channel mixer Selectable preemphasis for Aux channel Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs Complete SCART in/out switching matrix Two 48kHz I S inputs; one ansynchronous 5..50 kHz I S input, one 48 kHz I S output All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) ASTRA Digital Radio (ADR) together with DRP 3510A All NICAM standards Demodulation of the BTSC multiplex signal and the SAP channel Alignment free digital DBX noise reduction for BTSC Stereo and SAP Alignment free digital Micronas Noise Reduction (MNR) for BTSC Stereo and SAP BTSC stereo and EIA-J separation significantly better than spec. SAP and stereo detection for BTSC system Korean FM-Stereo A2 standard Alignment-free Japanese standard EIA-J Demodulation of the FM-Radio multiplex signal X X X
2 2 2
PRELIMINARY DATA SHEET
4408 X X X X X X X X X X X X X X
4418 X X X X X X X X X X X X X X X X X X
4428 X X X X X X X X X X X X X
4448 X X X X X X X X X X X X X
4458 X X X X X X X X X X X X X X X X X X
X
X X
X X
X X X X X X X X X X X X X X X X X
1.2. MSP 44x8G Version List
Version MSP 4408G MSP 4418G MSP 4428G MSP 4448G MSP 4458G Status planned planned planned planned available Description FM Stereo (A2) Version NICAM and FM Stereo (A2) Version NTSC Version (A2 Korea, BTSC with Micronas Noise Reduction (MNR), and Japanese EIA-J system) NTSC Version (A2 Korea, BTSC with DBX noise reduction, and Japanese EIA-J system) Global Version (all sound standards)
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PRELIMINARY DATA SHEET
MSP 44x8G
1.3. MSP 44x8G Versions and their Application Fields Table 1-1 provides an overview of TV sound standards that can be processed by the MSP 44x8G family. In addition, the MSP 44x8G is able to handle the terrestrial FM-Radio standard. With the MSP 44x8G, a complete multimedia receiver covering all TV sound standards together with terrestrial and satellite radio sound can be built; even ASTRA Digital Radio can be processed (with a DRP 3510A coprocessor).
Table 1-1: TV Stereo Sound Standards covered by the MSP 44x8G Family (details see Appendix A)
MSP Version 4408 System Position of Sound Carrier / MHz 5.5/5.7421875 B/G 5.5/5.85 L I 6.5/5.85 6.0/6.552 6.5/5.85 4418 6.5/6.2578125 D/K 6.5/6.7421875 4458 6.5/5.7421875 6.5 7.02/7.2 7.38/7.56 etc. 4.5/4.724212 4428/48 M 4.5 4.5 FM-Radio 10.7 FM-Stereo (A2, D/K2) FM-Stereo (A2, D/K3) FM-Mono FM-Stereo ASTRA Digital Radio (ADR) with DRP 3510A FM-Stereo (A2) FM-FM (EIA-J) BTSC-Stereo + SAP FM-Stereo Radio PAL SECAM-East currently no broadcast Poland FM-Mono/NICAM AM-Mono/NICAM FM-Mono/NICAM FM-Mono/NICAM FM-Stereo (A2, D/K1) PAL SECAM-L PAL PAL SECAM-East Scandinavia, Spain France UK, Hong Kong China, Hungary Slovak. Rep. Sound Modulation FM-Stereo (A2) Color System PAL Broadcast e.g. in: Germany
4408
Satellite
PAL
Europe Sat. ASTRA
NTSC NTSC NTSC
Korea Japan USA USA, Europe
33 34 39 MHz
4.5 9 MHz
SAW Filter Tuner Sound IF Mixer 1 Main Channel
Mono Vision Demodulator
SCART1 SCART Inputs SCART2 SCART3 SCART4
2 2 2 2 I2S3
MSP 44x8G
Aux Channel Aux Channel/ FM-Modulator 2 2 SCART1 SCART2
COMPOSITE Video
SCART Outputs
I2S1 ADR Digital Signal
I2S2
DolbyDigital/ MPEG
ADR Decoder
Fig. 1-2: Typical MSP 44x8G application
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Source Select
SCART DSP Input Select
SCART Output Select
8
ANA_IN1+ ANA_IN2+ AGC A D DEMODULATOR (incl. Carrier Mute) Deemphasis: 50/75 s DBX/MNR Panda1 FM/AM Prescale
(0Ehex)
Fig. 2-1 shows a simplified block diagram of the IC. The block diagram contains all features of the
2.1. Architecture of the MSP 44x8G Family
2. Functional Description
MSP 44x8G
Automatic Soundselect FM/AM Stereo or A Stereo or A Stereo or B 0 1 3 4 Main Channel Matrix
(08hex)
AVC*
Volume
D A
DACM_L
DACM_R
Decoded Standards: NICAM A2 AM BTSC EIA-J SAT FM-Radio ADR-Bus Interface
(29hex)
(00hex)
Deemphasis: J17
NICAM
Beeper
(14hex)
Prescale
(10hex)
Aux Channel Matrix
(09hex)
Volume
D A
DACA_L
Standard and Sound Detection
I2 C Read Register I2S Channel Matrix
Preemphasis
(34hex) (06hex)
DACA_R
I2S Interface
(0Bhex)
I2S_DA_OUT (sync. 48 kHz)
I2S_DA_IN1 (sync. 48 kHz)
I2S_CL I2S_WS
I2S Interface
I2S1 5 Prescale I2S2 6 Prescale I2S3 7 Prescale
(11hex) (12hex) (16hex)
Quasi-Peak Channel Matrix
(0Chex)
Quasi-Peak Detector
I2C Read Register
I2S_DA_IN2 (sync. 48 kHz)
I2S Interface
Note: *AVC location is programmable
I2S_CL3 I2S_WS3
I2S_DA_IN3 (async. 5-50 kHz)
I2S Interface
Synchronization / Interpolation
Mix1 Channel Matrix Mix2 Channel Matrix
Mix1 scale Mix2 scale (3B ) hex
(38hex)
(3Ahex)
AVC*
MSP 4458G. Other members of the MSP 44x8G family do not have the complete set of features, handling only a subset of the standards (see dashed block in Fig. 2-1).
15
(39hex)
(29hex)
A D
SCART 2 Prescale
(0Dhex)
SCART1 Channel Matrix
(0Ahex)
Volume
D A
SCART1_L/R
SC1_OUT_L
(07hex)
SCART2 Channel Matrix
(41hex)
Volume
D A
SCART2_L/R
SC1_OUT_R
PRELIMINARY DATA SHEET
(13hex)
(40hex)
SC1_IN_L SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L SC3_IN_R SC4_IN_L SC4_IN_R MONO_IN
SC2_OUT_L
SC2_OUT_R
Micronas
(13hex)
Fig. 2-1: Signal flow block diagram of the MSP 44x8G (input and output names correspond to pin names).
PRELIMINARY DATA SHEET
MSP 44x8G
FM-Satellite Sound: Demodulation of one or two FM carriers. Processing of high-deviation mono or narrow bandwidth mono, stereo, or bilingual satellite sound according to the ASTRA specification. FM-Stereo-Radio: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Detection and evaluation of the pilot carrier and AM demodulation of the (L-R)-carrier. The demodulator blocks of all MSP 44x8G versions have identical user interfaces. Even completely different systems like the BTSC and NICAM systems are controlled the same way. Standards are selected by means of MSP Standard Codes. Automatic processes handle standard detection and identification without controller interaction. The key features of the MSP 44x8G demodulator blocks are described below. Standard Selection: The controlling of the demodulator is minimized: All parameters, such as tuning frequencies or filter bandwidth, are adjusted automatically by transmitting one single value to the STANDARD SELECT register. For all standards, specific MSP standard codes are defined. Automatic Standard Detection: If the TV sound standard is unknown, the MSP 44x8G can automatically detect the actual standard, switch to that standard, and respond the actual MSP standard code. Automatic Carrier Mute: To prevent noise effects or FM identification problems in the absence of an FM carrier, the MSP 44x8G offers a carrier mute feature, which is activated automatically if the standard is selected by means of the STANDARD SELECT register. If no FM carrier is available at one of the two MSP demodulator channels, the corresponding demodulator output is muted.
2.2. MSP 44x8G Sound IF Processing 2.2.1. Analog Sound IF Input The input pins ANA_IN1+, ANA_IN2+, and ANA_IN- offer the possibility to connect two different sound IF (SIF) sources to the MSP 44x8G. The preselected sound IF signal is fed into an A/D-converter. An analog automatic gain circuit (AGC) allows a wide range of input levels. The highpass filters, formed by the coupling capacitors at pins ANA_IN1+ and ANA_IN2+ (see Section 7.3. "Application Circuit" on page 83), are sufficient in most cases to suppress video components. Some combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their outputs. In this case, further filtering is recommended.
2.2.2. Demodulator: Standards and Features The MSP 44x8G is able to demodulate all TV-sound standards worldwide including the digital NICAM system. Depending on the MSP 44x8G version, the following demodulation modes can be performed: A2 Systems: Detection and demodulation of two separate FM carriers (FM1 and FM2), demodulation and evaluation of the identification signal of carrier FM2. NICAM Systems: (Only possible in the MSP 4418G and MSP 4458G). Demodulation and decoding of the NICAM carrier, detection and demodulation of the analog FM or AM carrier. For D/K-NICAM, the FM carrier may have a maximum deviation of 384 kHz. Very high deviation FM-Mono: Detection and robust demodulation of one FM carrier with a maximum deviation of 540 kHz. BTSC-Stereo: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, AM demodulation of the (L-R)-carrier and detection of the SAP subcarrier. Processing of DBX noise reduction or Micronas Noise Reduction (MNR). BTSC-Mono + SAP: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, detection and FM demodulation of the SAP subcarrier. Processing of DBX noise reduction or Micronas Noise Reduction (MNR). Japan Stereo: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Demodulation and evaluation of the identification signal and FM demodulation of the (L-R)-carrier.
2.2.3. Preprocessing of Demodulator Signals All demodulated signals must be processed by a deemphasis filter and adjusted in level (analog signals must also be dematrixed). The correct deemphasis filters are already selected by setting the standard in the STANDARD SELECT register. The level adjustment has to be done by means of the FM/AM and NICAM prescale registers. The necessary dematrix function depends on the selected sound standard and the actual broadcasted sound mode (mono, stereo, or bilingual). It can be manually set by the FM Matrix Mode register or automatically set by the Automatic Sound Selection.
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2.2.4. Automatic Sound Select In the Automatic Sound Select mode, the dematrix function is automatically selected based on the identification information in the STATUS register. No I2C interaction is necessary when the broadcasted sound mode changes (e.g. from mono to stereo). The demodulator supports the identification check by switching between mono compatible standards (standards that have the same FM mono carrier) automatically and non-audible. If B/G-FM or B/G-NICAM is selected, the MSP will switch between these standards. The same action is performed for the standards: D/K1-FM, D/K2-FM, and D/K-NICAM. Switching is only done in the absence of any stereo or bilingual identification. If identification is found, the MSP keeps the detected standard. In case of high bit-error rates, the MSP 44x8G automatically falls back from digital NICAM sound to analog FM or AM mono. Table 2-1 on page 11 summarizes all actions that take place when Automatic Sound Select is switched on. To provide more flexibility, the Automatic Sound Select block prepares four different source channels of demodulated sound (Fig. 2-2). By choosing one of the four demodulator channels, the preferred sound mode can be selected by means of the Source Select registers, independent for all MSP-outputs. The following source channels of demodulated sound are defined: - "FM/AM" channel: Analog mono sound, stereo if available. In case of NICAM, analog mono only (FM or AM mono). - "Stereo or A/B" channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains both languages A (left) and B (right). - "Stereo or A" channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language A (on left and right). - "Stereo or B" channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language B (on left and right).
primary channel secondary channel NICAM A FM/AM
PRELIMINARY DATA SHEET
Fig. 2-2 and Table 2-2 show the source channel assignment of the demodulated signals in case of Automatic Sound Select mode for all sound standards (see Section 6.). Note: The analog primary input channel contains the signal of the mono FM/AM carrier or the L+R signal of the MPX carrier. The secondary input channel contains the signal of the second FM carrier, the L-R signal of the MPX carrier, or the SAP signal.
primary channel secondary channel NICAM A
FM/AM
FM/AM
0 Source Select
LS Ch. Matrix Output-Ch. Matrices must be set once to stereo
Prescale
Automatic Sound Select
Stereo or A/B
1
NICAM
Stereo or A
3
NICAM
Prescale
Stereo or B
4
SC2 Ch. Matrix
Fig. 2-2: Source channel assignment of demodulated signals in Automatic Sound Select Mode
2.2.5. Manual Mode Fig. 2-3 shows the source channel assignment of demodulated signals in case of manual mode. If manual mode is required, more information can be found in Section 6.7. "Demodulator Source Channels in Manual Mode" on page 80.
LS Ch. Matrix FM-Matrix FM/AM 0 Source Select Output-Ch. Matrices must be set according the standard
Prescale
NICAM NICAM (Stereo or A/B) 1
NICAM
Prescale
SC2 Ch. Matrix
Fig. 2-3: Source channel assignment of demodulated signals in Manual Mode
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PRELIMINARY DATA SHEET
MSP 44x8G
Table 2-1: Performed actions of the Automatic Sound Selection
Selected TV Sound Standard B/G-FM, D/K-FM, M-Korea, and M-Japan B/G-NICAM, L-NICAM, I-NICAM, and D/K-NICAM Performed Actions Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2-2. Identification is acquired after 500 ms. Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2-2. NICAM detection is acquired within 150 ms. In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches back to NICAM if possible. A hysteresis prevents periodical switching. B/G-FM, B/G-NICAM or D/K1-FM, D/K2-FM, D/K-NICAM Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and nonaudible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-Mono sound carrier. Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP keeps the corresponding standard. Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator source channels according to Table 2-2. Detection of the SAP carrier. Pilot detection is acquired after 200 ms. In the absence of SAP, the MSP switches to BTSC-Stereo if available. If SAP is detected, the MSP switches automatically to SAP (see Table 2-2).
BTSC-STEREO, FM Radio
BTSC-SAP
Table 2-2: Sound modes for the demodulator source channels with Automatic Sound Select
Source Channels in Automatic Sound Select Mode Broadcasted Sound Standard M-Korea B/G-FM D/K-FM M-Japan Selected MSP Standard Code3) 02 03, 081) 04, 05, 0B1) 30 Broadcasted Sound Mode FM/AM
(source select: 0)
Stereo or A/B
(source select: 1)
Stereo or A
(source select: 3)
Stereo or B
(source select: 4)
MONO STEREO BILINGUAL: Languages A and B
Mono Stereo Left = A Right = B analog Mono analog Mono analog Mono analog Mono Mono Stereo Mono Stereo Left = Mono Right = SAP Left = Mono Right = SAP Mono Stereo
Mono Stereo Left = A Right = B analog Mono NICAM Mono NICAM Stereo Left = NICAM A Right = NICAM B Mono Stereo Mono Stereo Left = Mono Right = SAP Left = Mono Right = SAP Mono Stereo
Mono Stereo A analog Mono NICAM Mono NICAM Stereo NICAM A Mono Stereo Mono Stereo Mono Mono Mono Stereo
Mono Stereo B analog Mono NICAM Mono NICAM Stereo NICAM B Mono Stereo Mono Stereo SAP SAP Mono Stereo
B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM
(with high deviation FM)
08, 032) 09 0A 0B, 042), 052) 0C
NICAM not available or error rate too high MONO STEREO BILINGUAL: Languages A and B
20, 21
MONO STEREO
20 BTSC 21
MONO+SAP STEREO+SAP MONO+SAP STEREO+SAP
FM Radio
40
MONO STEREO
1) 2) 3)
The Automatic Sound Select process will automatically switch to the mono compatible analog standard. The Automatic Sound Select process will automatically switch to the mono compatible digital standard. The MSP Standard Codes are defined in Table 3-7 on page 20.
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MSP 44x8G
2.3. Preprocessing for SCART and I2S Input Signals The SCART and I2S inputs need only be adjusted in level by means of the SCART and I2S prescale registers.
PRELIMINARY DATA SHEET
2.5. Audio Baseband Processing 2.5.1. Automatic Volume Correction (AVC) Different sound sources (e.g. terrestrial channels, SAT channels, or SCART) fairly often do not have the same volume level. Advertisements during movies usually have a higher volume level than the movie itself. This results in annoying volume changes. The AVC solves this problem by equalizing the volume level. In the standard configuration the AVC block is located in the main channel. Alternatively, the AVC function can be moved to the mixer path. To prevent clipping, the AVC's gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low-level inputs. The decay time is programmable by the AVC register (see page 29). For input signals ranging from -24 dBr to 0 dBr, the AVC maintains a fixed output level of -18 dBr. Fig. 2-4 shows the AVC output level versus its input level. For prescale and volume registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. This is - SCART input/output 0 dBr = 2.0 Vrms - Main and Aux output 0 dBr = 1.4 Vrms
2.4. Source Selection and Output Channel Matrix The Source Selector makes it possible to distribute all source signals (one of the demodulator source channels, SCART, or I2S input) to the desired output channels (Main, Aux, etc.). All input and output signals can be processed simultaneously. Each source channel is identified by a unique source address. For each output channel, the output channel matrix can be set to sound A, sound B, stereo, or mono. If Automatic Sound Select is on, the output channel matrix can stay fixed to stereo (transparent) for demodulated signals.
2.4.1. Mixing Unit Any source can be selected as the input for the two channels of the Mixing unit. The mixer channel matrices and the scaling factors can be programmed separately for each channel. After adding up both channels, the signal is fed back and is available as source 15 (Mix output) of the Source Selector.
output level [dBr]
-12 -18 -24
-30
-24
-18
-12
-6
0
+6
input level [dBr] Fig. 2-4: Simplified AVC characteristics
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PRELIMINARY DATA SHEET
MSP 44x8G
2.7.1. Synchronous I2S-Interface(s) The synchronous I2S bus interface consists of the pins: - I2S_DA_IN1, I2S_DA_IN2/3 (I2S_DA_IN2 in PQFP80 package): I2S serial data input, 16, 18...32 bits per sample. - I2S_DA_OUT: I2S serial data output, 16, 18...32 bits per sample. - I2S_CL: I2S serial clock. - I2S_WS: I2S word strobe signal defines the left and right sample. If the MSP 44x8G serves as the master on the I2S interface, the clock and word strobe lines are driven by the MSP. In this mode, only 16, 32 bits per sample can be selected. In slave mode, these lines are input to the MSP 44x8G and the MSP clock is synchronized to 384 times the I2S_WS rate (48 kHz). NICAM operation is not possible in slave mode. An I2S timing diagram is shown in Fig. 4-22 on page 59. 2.7.2. Asynchronous I2S-Interface The asynchronous I2S slave interface allows the reception of digital stereo signals with arbitrary sample rates from 5 to 50 kHz. The synchronization is performed by means of an adaptive sample rate converter. No oversampling clock is required. The following pins are used for the asynchronous I2S bus interface: - I2S_WS3 (serves only as input) - I2S_CL3 (serves only as input) - I2S_DA_IN2/3 (I2S_DA_IN3 in PQFP80 package). The interface accepts I2S-input streams with MSB first and with sample widths of 16,18...32 bits. With left/ right alignment and wordstrobe timing polarity, there are additional parameters available for the adaption to a variety of formats in the I2S-CONFIG register (see page 24).
2.5.2. Main and Aux Outputs The Main and Aux output channels are adjustable in volume. A square wave beeper with adjustable frequency and volume can be added to them.
2.5.3. Quasi-Peak Detector The Quasi-Peak Readout register can be used to read out the quasi-peak level of any input source. The feature is based on following filter time constants: - attack time: 1.3 ms - decay time: 37 ms
2.6. SCART Signal Routing 2.6.1. SCART DSP In and SCART Out Select The SCART DSP Input Select and SCART Output Select blocks include full matrix switching facilities. To design a TV set with four pairs of SCART-inputs and two pairs of SCART-outputs, no external switching hardware is required. The switches are controlled by the ACB user register (see page 31).
2.6.2. Stand-by Mode If the MSP 44x8G is switched off by first pulling STANDBYQ low and then (after >1 s delay) switching off the 5-V, but keeping the 8-V power supply (`Standby'-mode), the SCART switches maintain their position and function. This allows the copying from selected SCART-inputs to SCART-outputs in the TV set's stand-by mode. In case of power on or starting from stand-by (see details on the power-up sequence in Fig. 4-20 on page 56), all internal registers except the ACB register (page 31) are reset to the default configuration (see Table 3-5 on page 18). The reset position of the ACB register becomes active after the first I2C transmission into the Baseband Processing part (subaddress 12hex). By transmitting the ACB register first, the reset state can be redefined. 2.7. I2S Bus Interfaces The MSP 44x8G has two kinds of interfaces: synchronous master/slave input/output interfaces running on 48 kHz and an asynchronous slave interface. The interfaces accept a variety of formats with different sample width, bit-orientation, and wordstrobe timing. All I2S options are set by means of the MODUS or I2S_CONFIG register.
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2.8. ADR Bus Interface For the ASTRA Digital Radio System (ADR), the MSP 4408G, MSP 4418G, and MSP 4458G performs preprocessing such as carrier selection and filtering. Via the 3-line ADR-bus, the resulting signals are transferred to the DRP 3510A coprocessor, where the source decoding is performed. To be prepared for an upgrade to ADR with an additional DRP board, the following lines of MSP 44x8G should be provided on a feature connector: - AUD_CL_OUT - I2S_DA_IN1, 2, or 3 - I2S_DA_OUT, I2S_WS, I2S_CL - ADR_CL, ADR_WS, ADR_DA For more details, please refer to the DRP 3510A data sheet. 2.10. Preemphasis
PRELIMINARY DATA SHEET
When using the Aux output for feeding an external modulator, a preemphasis can be applied to the right channel. The signal is scaled down by -3 dB. An overmodulation protection is included in the algorithm which limits the output signal to 0 dBFS. Due to the nature of a preemphasis, its gain at high frequencies exceeds 3 dB. Thus, even with 0 dB input signals and prescaler / volume set to 0 dB, clipping can occur. There are three modes present: preemphasis off, 50 s, and 75 s. (see Table 3-11on page 29) for the register settings.
2.11. Clock PLL Oscillator and Crystal Specifications The MSP 44x8G derives all internal system clocks from the 18.432 MHz oscillator. In NICAM or in I2SSlave mode of the synchronous interface, the clock is phase-locked to the corresponding source. Therefore, it is not possible to use NICAM and I2S-Slave mode of the synchronous interface at the same time. For proper performance, the MSP clock oscillator requires a 18.432-MHz crystal. Note that for the phase-locked modes (NICAM, I2S-Slave), crystals with tighter tolerance are required. Please note also, that the asynchronous I2S3 slave interface uses a different locking mechanism and does not require tighter crystal tolerances. Remark on using the crystal: External capacitors at each crystal pin to ground are required. They are necessary for tuning the open-loop frequency of the internal PLL and for stabilizing the frequency in closed-loop operation. The higher the capacitors, the lower the resulting clock frequency. The nominal free running frequency should match 18.432 MHz as closely as possible. Clock measurements should be done at pin AUD_CL_OUT. This pin must be activated for this purpose (see MODUS register on page 23).
2.9. Digital Control I/O Pins and Status Change Indication The static level of the digital input/output pins D_CTR_I/O_0/1 is switchable between HIGH and LOW via the I2C-bus by means of the ACB register (see page 31). This enables the controlling of external hardware switches or other devices via I2C-bus. The digital input/output pins can be set to high impedance by means of the MODUS register (see page 23). In this mode, the pins can be used as input. The current state can be read out of the STATUS register (see page 25). Optionally, the pin D_CTR_I/O_1 can be used as an interrupt request signal to the controller, indicating any changes in the read register STATUS. This makes polling unnecessary, I2C bus interactions are reduced to a minimum (see "STATUS Register" on page 25 and "MODUS Register" on page 23).
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PRELIMINARY DATA SHEET
MSP 44x8G
Due to the internal architecture of the MSP 44x8G, the IC cannot react immediately to an I2C request. The typical response time is about 0.3 ms. If the MSP cannot accept another complete byte of data until it has performed some other function (for example, servicing an internal interrupt), it will hold the clock line I2C_CL low to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by "Wait" in Section 3.1.3. The maximum wait period of the MSP during normal operation mode is less than 1 ms. Internal hardware error handling: In case of any internal hardware error (e.g. interruption of the power supply of the MSP), the MSP's wait period is extended to 1.8 ms. After this time period elapses, the MSP releases data and clock lines. Indication and solving of the error status: To indicate the error status, the remaining acknowledge bits of the actual I2C-protocol will be left high. Additionally, bit[14] of CONTROL is set to one. The MSP can then be reset via the I2C bus by transmitting the reset condition to CONTROL. Indication of reset: Any reset, even caused by an unstable reset line etc., is indicated in bit[15] of CONTROL. A general timing diagram of the I2C Bus is shown in Fig. 4-21 on page 57.
3. Control Interface 3.1. I2C Bus Interface 3.1.1. Device and Subaddresses The MSP 44x8G is controlled via the I2C bus slave interface. The IC is selected by transmitting one of the MSP 44x8G device addresses. In order to allow up to three MSP ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left open, the MSP 44x8G responds to different device addresses. A device address pair is defined as a write address and a read address (see Table 3-1). Writing is done by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the write device address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address and reading two bytes of data. Refer to Section 3.1.2. for the I2C bus protocol and to Section 3.4. "Programming Tips" on page 34 for proposals of MSP 44x8G I2C telegrams. See Table 3-2 for a list of available subaddresses. Besides the possibility of hardware reset, the MSP can also be reset by means of the RESET bit in the CONTROL register by the controller via I2C bus.
Table 3-1: I2C Bus Device Addresses
ADR_SEL Mode MSP device address Write 80hex Low Read 81hex Write 84hex High Read 85hex Write 88hex Left Open Read 89hex
Table 3-2: I2C Bus Subaddresses
Name CONTROL TEST WR_DEM RD_DEM WR_DSP RD_DSP Binary Value 0000 0000 0000 0001 0001 0000 0001 0001 0001 0010 0001 0011 Hex Value 00 01 10 11 12 13 Mode Read/Write Write Write Write Write Write Function Write: Software reset of MSP (see Table 3-3) Read: Hardware error status of MSP only for internal use write address demodulator read address demodulator write address DSP read address DSP
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3.1.2. Description of CONTROL Register
PRELIMINARY DATA SHEET
Table 3-3: CONTROL as a Write Register
Name CONTROL Subaddress 00hex Bit[15] (MSB) 1 : RESET 0 : normal Bits[14:0] 0
Table 3-4: CONTROL as a Read Register
Name CONTROL Subaddress 00hex Bit[15] (MSB) Reset status after last reading of CONTROL: 0 : no reset occured 1 : reset occured Bit[14] Internal hardware status: 0 : no error occured 1 : internal error occured Bits[13:0] not of interest
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be read once to be reset.
3.1.3. Protocol Description Write to DSP or Demodulator
S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte- ACK data-byte ACK P high low high low
Read from DSP or Demodulator
S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK S high low read device address Wait ACK data-byte- ACK data-byte NAK P high low
Write to Control or Test Registers
S Wait write device address ACK sub-addr ACK data-byte ACK data-byte ACK P high low
Note: S = P= ACK = NAK =
I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray) Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate `End of Read' or from MSP indicating internal error state Wait = I2C-Clock line is held low, while the MSP is processing the I2C command.
I2C_DA S I2C_CL
1 0 P
Fig. 3-1: I2C bus protocol (MSB first; data must be stable while clock is high)
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PRELIMINARY DATA SHEET
MSP 44x8G
3.2. Start-Up Sequence: Power-Up and I2C Controlling After POWER ON or RESET (see Fig. 4-20 on page 56), the IC is in an inactive state. All registers are in the reset position (seeTable 3-5 and Table 3-6), the analog outputs are muted. The controller has to initialize all registers for which a non-default setting is necessary.
3.1.4. Proposals for General MSP 44x8G I2C Telegrams 3.1.4.1. Symbols daw dar < > aa dd write device address (80hex, 84hex or 88hex) read device address (81hex, 85hex or 89hex) Start Condition Stop Condition Address Byte Data Byte
3.3. MSP 44x8G Programming Interface 3.1.4.2. Write Telegrams

3.3.1. User Registers Overview
write to CONTROL register write data into demodulator write data into DSP
3.1.4.3. Read Telegrams
read data from demodulator read data from DSP
The MSP 44x8G is controlled by means of user registers. The complete list of all user registers is given in the following tables. The registers are partitioned into the demodulator section (subaddress 10hex for writing, 11hex for reading) and the baseband processing sections (subaddress 12hex for writing, 13hex for reading). Write and read registers are 16-bit wide, whereby the MSB is denoted bit[15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, with the most significant byte transferred first). All write registers, except the demodulator write registers, are readable. Unused parts of the 16-bit write registers must be zero. Addresses not given in this table must not be written. An overview of all MSP 44x8G write registers is shown in Table 3-5; all read registers are given in Table 3-6. Additional read and write registers, together with a detailed description of the manual mode, can be found in the "Appendix B: Manual Mode" on page 73.
3.1.4.4. Examples
<80 <80 <80 <80 <80 00 00 10 11 12 80 00 00 02 00 00> RESET MSP statically 00> Clear RESET 20 00 03> Set demodulator to stand. 03hex 00 <81 dd dd> Read STATUS 08 01 20> Set main channel
source to NICAM and Matrix to STEREO
More examples of typical application protocols are listed in Section 3.4. "Programming Tips" on page 34.
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Table 3-5: List of MSP 44x8G Write Registers
Write Register Address (hex) Bits Description and Adjustable Range
PRELIMINARY DATA SHEET
Reset
See Page
I2C Subaddress = 10hex ; Registers are not readable STANDARD SELECT MODUS
2
00 20 00 30
[15:0] [15:0]
Initial Programming of complete Demodulator Demodulator, Automatic and I2S options
2
00 00 00 00
21 22
I C Subaddress = 12hex ; Registers are all readable by using I C Subaddress = 13hex Volume main channel 00 00 [15:8] [7:5] [4:0] Volume Aux channel 00 06 [15:8] [7:5] [4:0] Volume SCART1 output channel Main source select Main channel matrix Aux source select Aux channel matrix SCART1 source select SCART1 channel matrix I S source select I2S channel matrix Quasi-peak detector source select Quasi-peak detector matrix Prescale SCART input Prescale FM/AM FM matrix Prescale NICAM Prescale I2S3 00 10 00 11 00 12 00 13 00 14 00 16 00 29 00 34 00 38 00 0D 00 0E 00 0C
2
[+12 dB ... -114 dB, MUTE] 1/8 dB Steps must be set to 0 [+12 dB ... -114 dB, MUTE] 1/8 dB Steps must be set to 0 [+12 dB ... -114 dB, MUTE] [FM/AM, NICAM, SCART, I2S1..3, Mix output] [SOUNDA, SOUNDB, STEREO, MONO] [FM/AM, NICAM, SCART, I2S1..3, Mix output] [SOUNDA, SOUNDB, STEREO, MONO] [FM/AM, NICAM, SCART, I S1..3, Mix output] [SOUNDA, SOUNDB, STEREO, MONO] [FM/AM, NICAM, SCART, I S1..3, Mix output] [SOUNDA, SOUNDB, STEREO, MONO] [FM/AM, NICAM, SCART, I2S1..3, Mix output] [SOUNDA, SOUNDB, STEREO, MONO] [00hex ... 7Fhex] [00hex ... 7Fhex] [NO_MAT, GSTEREO, KSTEREO] [00hex ... 7Fhex] [00hex ... 7Fhex] [00hex ... 7Fhex] Bits [15:0] [00hex ... 7Fhex]/[00hex ... 7Fhex] [00hex ... 7Fhex] [off, on, decay time] [OFF, 50s, 75s] [FM/AM, NICAM, SCART, I2S1..3, Mix output] [SOUNDA, SOUNDB, STEREO, MONO] [FM/AM, NICAM, SCART, I2S1..3, Mix output] [SOUNDA, SOUNDB, STEREO, MONO] [00hex ... 7Fhex] [00hex ... 7Fhex]
2 2
MUTE 000bin 00000bin MUTE 000bin 00000bin MUTE FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA 00hex 00hex NO_MAT 00hex 10hex 10hex 00hex 00/00hex 10hex off OFF FM/AM SOUNDA FM/AM SOUNDA 00hex 00hex
29
29
00 07 00 08
[15:8] [15:8] [7:0]
30 28 28 28 28 28 28 28 28 28 28 27 26 27 27 27 27 31 32 27 29 29 28 28 28 28 32 32
00 09
[15:8] [7:0]
00 0A
[15:8] [7:0]
00 0B
[15:8] [7:0] [15:8] [7:0] [15:8] [15:8] [7:0] [15:8] [15:8] [15:8] [15:0] [15:0] [15:8] [15:8] [15:8] [15:8] [7:0]
Prescale I2S2 SCART switches and D_CTR_I/O Beeper Prescale I2S1 AVC: Automatic Volume Correction Aux Preemphasis on right channel Mix1 source select Mix1 channel matrix Mix2 source select Mix2 channel matrix Scale Mix1 Scale Mix2
00 39
[15:8] [7:0]
00 3A 00 3B
[15:8] [15:8]
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PRELIMINARY DATA SHEET
MSP 44x8G
Table 3-5: List of MSP 44x8G Write Registers, continued
Write Register Volume SCART2 output channel SCART2 source select SCART2 channel matrix Address (hex) 00 40 00 41 Bits [15:8] [15:8] [7:0] Description and Adjustable Range [+12 dB ... -114 dB, MUTE] [FM/AM, NICAM, SCART, I S1..3, Mix output] [SOUNDA, SOUNDB, STEREO, MONO]
2
Reset 00hex FM SOUNDA
See Page 30 28 28
Table 3-6: List of MSP 44x8G Read Registers
Read Register Address (hex) Bits Description and Adjustable Range See Page
I2C Subaddress = 11hex ; Registers are not writable STANDARD RESULT STATUS 00 7E 02 00 [15:0] [15:0] Result of Automatic Standard Detection (see Table 3-8) Monitoring of settings e.g. Stereo, Mono, Mute, D_CTR_I/O etc. . 25 25
I2C Subaddress = 13hex ; Registers are not writable Quasi peak readout left Quasi peak readout right MSP hardware version code MSP major revision code MSP product code MSP ROM version code 00 1F 00 19 00 1A 00 1E [15:0] [15:0] [15:8] [7:0] [15:8] [7:0] [00hex ... 7FFFhex]16 bit two's complement [00hex ... 7FFFhex]16 bit two's complement [00hex ... FFhex] [00hex ... FFhex] [00hex ... FFhex] [00hex ... FFhex] 33 33 33 33 33 33
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3.3.2. Description of User Registers Table 3-7: Standard Codes for STANDARD SELECT register MSP Standard Code (Data in hex) TV Sound Standard
PRELIMINARY DATA SHEET
Sound Carrier Frequencies in MHz
MSP 44x8G Version
Automatic Standard Detection 00 01 Start Automatic Standard Detection Standard Selection 00 02 00 03 00 04 00 05 00 06 M-Dual FM-Stereo B/G-Dual FM-Stereo1) D/K1-Dual FM-Stereo2) D/K2-Dual FM-Stereo2) D/K-FM-Mono with HDEV33), not detectable by Automatic Standard Detection, for China HDEV33) SAT-Mono (i.e. Eutelsat, see Table 6-12) D/K3-Dual FM-Stereo B/G-NICAM-FM1) L-NICAM-AM I-NICAM-FM D/K-NICAM-FM2) D/K-NICAM-FM with HDEV24), not detectable by Automatic Standard Detection, for China D/K-NICAM-FM with HDEV33), not detectable by Automatic Standard Detection, for China BTSC-Stereo BTSC-Mono + SAP EIA-J Japan Stereo FM-Stereo Radio SAT-Mono (see Table 6-12) SAT-Stereo (see Table 6-12) SAT ADR (Astra Digital Radio) 4.5 10.7 6.5 7.02/7.20 6.12 4448, 4458 4438, 4448, 4458 4408, 4418, 4458 4408, 4418, 4458 4408, 4418, 4458 4.5/4.724212 5.5/5.7421875 6.5/6.2578125 6.5/6.7421875 6.5 4408, 4418, 4448, 4458 4408, 4418, 4458 all
00 07 00 08 00 09 00 0A 00 0B 00 0C 00 0D 00 20 00 21 00 30 00 40 00 50 00 51 00 60
1) 2) 3) 4)
6.5/5.7421875 5.5/5.85 6.5/5.85 6.0/6.552 6.5/5.85 6.5/5.85 6.5/5.85 4.5
4408, 4418, 4458 4418, 4458
4418, 4458 4438, 4448, 4458
In case of Automatic Sound Select, the B/G-codes 3hex and 8hex are equivalent. In case of Automatic Sound Select, the D/K-codes 4hex, 5hex, 7hex and Bhex are equivalent. HDEV3: Max. FM deviation must not exceed 540 kHz HDEV2: Max. FM deviation must not exceed 360 kHz
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PRELIMINARY DATA SHEET
MSP 44x8G
As long as the STANDARD RESULT register contains a value greater than 07 FFhex, the Automatic Standard Detection is still active. During this period, the MODUS and STANDARD SELECT register must not be written. The STATUS register will be updated when the Automatic Standard Detection has finished. If a present sound standard is impossible for a specific MSP version, it detects and switches to the analog mono sound of this standard. Example: The MSPs 4438G and 4448G will detect a B/G-NICAM signal as standard 3 and will switch to the analog FMMono sound.
3.3.2.1. STANDARD SELECT Register The TV sound standard of the MSP 44x8G demodulator is determined by the STANDARD SELECT register. There are two ways to use the STANDARD SELECT register: - Setting up the demodulator for a TV sound standard by sending the corresponding standard code with a single I2C-Bus transmission. - Starting the Automatic Standard Detection for terrestrial TV standards. This is the most comfortable way to set up the demodulator. Within 0.5 s, the detection and set-up of the actual TV sound standard is performed. The detected standard can be read out of the STANDARD RESULT register by the control processor. This feature is recommended for the primary set-up of a TV set. Outputs should be muted during Automatic Standard Detection. The Standard Codes are listed in Table 3-7. Selecting a TV sound standard via the STANDARD SELECT register initializes the demodulator. This includes: AGC, tuning frequency, band-pass filters, demodulation mode (FM, AM, or NICAM), carrier mute, deemphasis, and identification mode. If a present sound standard is impossible for a specific MSP version, it switches to the analog mono sound of this standard. In that case, stereo or bilingual processing will not be possible. For a complete setup of the TV sound processing from analog IF input to the source selection, the following transmissions are necessary: MODUS register, STANDARD SELECT register, prescale values, FM matrix. Note: The FM matrix is set automatically if Automatic Sound Select is active (MODUS[0]=1). In this case, the FM matrix will be initialized with "Sound A Mono". During operation, the FM matrix will be automatically selected according to the actual identification information.
Table 3-8: Results of the Automatic Standard Detection
Broadcasted Sound Standard Automatic Standard Detection could not find a sound standard B/G-FM B/G-NICAM I FM-Radio M-FM EIA-J BTSC STANDARD RESULT Register Read 007Ehex 0000hex
0003hex 0008hex 000Ahex 0040hex 0002hex (if MODUS[14,13]=00) 0020hex (if MODUS[14,13]=01) 0030hex (if MODUS[14,13]=10)
L-AM D/K1 D/K2 L-NICAM D/K-NICAM Automatic Standard Detection still active
0009hex (if MODUS[12]=0) 0004hex (if MODUS[12]=1) 0009hex (if MODUS[12]=0) 000Bhex (if MODUS[12]=1)
3.3.2.2. STANDARD RESULT Register If Automatic Standard Detection is selected in the STANDARD SELECT register, status and result of the Automatic Standard Detection process can be read out of the STANDARD RESULT register. The possible results are based on the mentioned Standard Code and are listed in Table 3-8. In cases where no sound standard has been detected (no standard present, too much noise, strong interferers, etc.) the STANDARD RESULT register contains 00 00hex. In that case, the controller has to start further actions (for example, set the standard according to a preference list or by manual input).
>07FFhex
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3.3.2.3. Write Registers on I2C Subaddress 10hex Table 3-9: Write Registers on I2C Subaddress 10hex Register Address Function
PRELIMINARY DATA SHEET
Name
STANDARD SELECTION 00 20hex STANDARD SELECTION Register Defines TV Sound or FM-Radio Standard bit[15:0] 00 01hex 00 02hex ... 00 60hex start Automatic Standard Detection Standard Codes (see Table 3-7)) STANDARD_SEL
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PRELIMINARY DATA SHEET
MSP 44x8G
Table 3-9: Write Registers on I2C Subaddress 10hex, continued Register Address MODUS 00 30hex MODUS Register General MSP 44x8G Options bit[15] bit[14:13] 0 1 2 3 0 undefined, must be 0 detected 4.5 MHz carrier is interpreted as:1) standard M (Korea) standard M (BTSC) standard M (Japan) Carrier at 4.5 MHz is ignored (chroma carrier) MODUS Function Name
Preference in Automatic Standard Detection: bit[12] 0 1 bit[11:9] bit[8] bit[7] bit[6] 0 1 bit[5] bit[4] bit[3] 0 0/1 0/1 0 0/1 0/1 detected 6.5 MHz carrier is interpreted as:1) standard L (SECAM) standard D/K1, D/K2, or D/K NICAM undefined, must be 0 ANA_IN_1+/ANA_IN_2+; select analog sound IF input pin active/tristate state of audio clock output pin AUD_CL_OUT word strobe alignment (synchronous I2S) WS changes at data word boundary WS changes one clock cycle in advance master/slave mode of I2S interface (must be set to 0 (= Master) in case of NICAM mode) active/tristate state of I2S output pins state of digital output pins D_CTR_I/O_0 and _1 active: D_CTR_I/O_0 and _1 are output pins (can be set by means of the ACB register. see also: MODUS[1]) tristate: D_CTR_I/O_0 and _1 are input pins (level can be read out of STATUS[4,3]) undefined, must be 0 disable/enable STATUS change indication by means of the digital I/O pin D_CTR_I/O_1 Necessary condition: MODUS[3] = 0 (active) off/on: Automatic Sound Select
1 bit[2] bit[1] 0 0/1
bit[0]
1)
0/1
Valid at the next start of Automatic Standard Detection.
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Table 3-9: Write Registers on I2C Subaddress 10hex, continued Register Address 0040hex Function I2S Configuration Register (not mentioned bit combinations must not be used) bit[15:12] bit[11] 0 1 bit[10] 1 0 bit[9] 0 1 bit[8:2] bit[1:0] 00 01 1x 0 0 undefined, must be set to 0 I2S Data alignment (I2S_3) left aligned right aligned word strobe polarity (I2S_3) 0 = right, 1 = left 1 = right, 0 = left word strobe alignment (asynchronous I2S_3) WS changes at data word boundary WS changes one clock cycle in advance undefined, must be set to 0
PRELIMINARY DATA SHEET
Name I2S_CONFIG
I2S_CL frequency and I2S_DA_OUT sample length 2 * 16Bit (1.536MHz Clk) 2 * 32Bit (3.072MHz Clk) undefined, must not be used
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PRELIMINARY DATA SHEET
MSP 44x8G
3.3.2.4. Read Registers on I2C Subaddress 11hex Table 3-10: Read Registers on I2C Subaddress 11hex Register Address Function Name
STANDARD RESULT 00 7Ehex STANDARD RESULT Register Readback of the detected TV Sound or FM-Radio Standard bit[15:0] 00 00hex Automatic Standard Detection could not find a sound standard MSP Standard Codes (see Table 3-8) STANDARD_RES
00 02hex ... 00 40hex >07 FFhex Automatic Standard Detection still active STATUS 02 00hex STATUS Register
STATUS
Contains all user relevant internal information about the status of the MSP bit[15:10] bit[8] bit[7] bit[6] bit[5,9] 0/1 0/1 0/1 00 01 10 11 undefined "1" indicates bilingual sound mode or SAP present "1" indicates independent mono sound (only for NICAM on MSP 4418G and MSP 4458G) mono/stereo indication analog sound standard (FM or AM) active this pattern will not occur digital sound (NICAM) available (MSP 4418G and MSP 4458G only) bad reception condition of digital sound (NICAM) due to: a. high error rate b. unimplemented sound code c. data transmission only low/high level of digital I/O pin D_CTR_I/O_1 low/high level of digital I/O pin D_CTR_I/O_0 detected secondary carrier (2nd A2 or SAP carrier) no secondary carrier detected detected primary carrier (Mono or MPX carrier) no primary carrier detected undefined
bit[4] bit[3] bit[2] bit[1] bit[0]
0/1 0/1 0 1 0 1
If STATUS change indication is activated by means of MODUS[1]: Each change in the STATUS register sets the digital I/O pin D_CTR_I/O_1 to high level. Reading the STATUS register resets D_CTR_I/O_1.
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3.3.2.5. Write Registers on I2C Subaddress 12hex Table 3-11: Write Registers on I2C Subaddress 12hex Register Address Function
PRELIMINARY DATA SHEET
Name
PREPROCESSING 00 0Ehex FM/AM Prescale bit[15:8] 00hex... 7Fhex 00hex Defines the input prescale gain for the demodulated FM or AM signal off (RESET condition) PRE_FM
For all FM modes except satellite FM, the combinations of prescale value and FM deviation listed below lead to internal full scale. FM mode bit[15:8] 7Fhex 48hex 30hex 24hex 18hex 13hex 28 kHz FM deviation 50 kHz FM deviation 75 kHz FM deviation 100 kHz FM deviation 150 kHz FM deviation 180 kHz FM deviation (limit)
FM high deviation mode (HDEV2, MSP Standard Code = Chex) bit[15:8] 30hex 14hex 150 kHz FM deviation 360 kHz FM deviation (limit)
FM very high deviation mode (HDEV3, MSP Standard Code = 6) bit[15:8] 20hex 1Ahex 450 kHz FM deviation 540 kHz FM deviation (limit)
Satellite FM with adaptive deemphasis bit[15:8] 10hex recommendation
AM mode (MSP Standard Code = 9) bit[15:8] 7Chex recommendation for SIF input levels from 0.1 Vpp to 0.8 Vpp (Due to the AGC switched on, the AM-output level remains stable and independent of the actual SIF-level in the mentioned input range)
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PRELIMINARY DATA SHEET
MSP 44x8G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address
(continued)
Function FM Matrix Modes Defines the dematrix function for the demodulated FM signal bit[7:0] 00hex 01hex 02hex 03hex 04hex no matrix (used for bilingual and unmatrixed stereo sound) German stereo (Standard B/G) Korean stereo (also used for BTSC, EIA-J, and FM Radio) sound A mono (left and right channel contain the mono sound of the FM/AM mono carrier) sound B mono (i.e. SAP)
Name FM_MATRIX
00 0Ehex
In case of Automatic Sound Select, the FM Matrix Mode is set automatically, i.e. the low-part of any I2C transmission to the register 00 0Ehex is ignored. To enable a Forced Mono Mode for all analog stereo systems by overriding the internal pilot or identification evaluation, the following steps must be transmitted: 1. MODUS with bit[0] = 0 (Automatic Sound Select off) 2. FM Presc./Matrix with FM Matrix = Sound A Mono (SAP: Sound B Mono) 3. Select FM/AM source channel, with channel matrix set to "Stereo" (transparent) 00 10hex NICAM Prescale Defines the input prescale value for the digital NICAM signal bit[15:8] 00hex ... 7Fhex prescale gain examples: 00hex 20hex 5Ahex 7Fhex 00 16hex 00 12hex 00 11hex I2S1 Prescale I2S2 Prescale I2S3 Prescale Defines the input prescale value for digital I2S input signals bit[15:8] 00hex ... 7Fhex prescale gain examples: off 00hex 0 dB gain (recommendation) 10hex +18 dB gain (maximum gain) 7Fhex 00 0Dhex SCART Input Prescale Defines the input prescale value for the analog SCART input signal bit[15:8] 00hex ... 7Fhex prescale gain examples: off 00hex 0 dB gain (2 VRMS input leads to digital full scale) 19hex +14 dB gain (400 mVRMS input leads to digital full scale) 7Fhex PRE_SCART off 0 dB gain 9 dB gain (recommendation) +12 dB gain (maximum gain) PRE_I2S1 PRE_I2S2 PRE_I2S3 PRE_NICAM
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Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address Function
PRELIMINARY DATA SHEET
Name
SOURCE SELECT AND OUTPUT CHANNEL MATRIX 00 08hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex 00 38hex 00 39hex Source for: Main Output Aux Output SCART1 DA Output SCART2 DA Output I2S Output Quasi-Peak Detector Mix1 Input Mix2 Input bit[15:8] 0 1 3 4 2 5 6 7 15 "FM/AM": demodulated FM or AM mono signal "Stereo or A/B": demodulator Stereo or A/B signal "Stereo or A": demodulator Stereo Sound or Language A (only defined for Automatic Sound Select) "Stereo or B": demodulator Stereo Sound or Language B (only defined for Automatic Sound Select) SCART input I2S1 input I2S2 input I2S3 input Mix output SRC_MAIN SRC_AUX SRC_SCART1 SRC_SCART2 SRC_I2S SRC_QPEAK SRC_MIX1 SRC_MIX2
For demodulator sources, see Table 2-2. 00 08hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex 00 38hex 00 39hex Matrix Mode for: Main Output Aux Output SCART1 DA Output SCART2 DA Output I2S Output Quasi-Peak Detector Mix1 Input Mix2 Input bit[7:0] 00hex 10hex 20hex 30hex Sound A Mono (or Left Mono) Sound B Mono (or Right Mono) Stereo (transparent mode) Mono (sum of left and right inputs divided by 2) More modes are listed in Section 6.5.1. MAT_MAIN MAT_AUX MAT_SCART1 MAT_SCART2 MAT_I2S MAT_QPEAK MAT_MIX1 MAT_MIX2
In Automatic Sound Select mode, the demodulator source channels are set according to Table 2-2. Therefore, the matrix modes of the corresponding output channels should be set to "Stereo" (transparent).
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PRELIMINARY DATA SHEET
MSP 44x8G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
MAIN AND AUX PROCESSING 00 00hex 00 06hex Volume Main Volume Aux bit[15:8] volume table with 1 dB step size +12 dB (maximum volume) 7Fhex 7Ehex +11 dB ... 74hex +1 dB 73hex 0 dB -1 dB 72hex ... 02hex -113 dB 01hex -114 dB 00hex Mute (reset condition) Fast Mute (needs about 75 ms until the signal is comFFhex pletely ramped down) higher resolution volume table 0 +0 dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table not used must be set to 0 VOL_MAIN VOL_AUX
bit[7:5]
bit[4:0]
With large scale input signals, positive volume settings may lead to signal clipping. The MSP 44x8G Main and Aux volume function is divided into a digital and an analog section. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. To turn volume on again, the volume step that has been used before Fast Mute was activated must be transmitted. 0029hex Automatic Volume Correction (AVC) bit[15] bit[14] bit[13:12] bit[11:8] 0 1 0 1 0 8 4 2 1 AVC off, reset of internal variables AVC on AVC in Main path AVC in Mixer path must be set to zero 8 s decay time 4 s decay time (recommended) 2 s decay time 20 ms decay time (should be used for approx. 100 ms after channel change) AVC_DECAY AVC
00 34hex
Preemphasis Aux Channel bit[15:8] 00hex 7Fhex FFhex Preemphasis OFF Preemphasis 50 s (-3 dB scaling) Preemphasis 75 s (-3 dB scaling)
PREEMP_AUX
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Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address Function
PRELIMINARY DATA SHEET
Name
SCART OUTPUT CHANNEL 00 07hex 00 40hex Volume SCART1 Output Channel Volume SCART2 Output Channel bit[15:8] volume table with 1 dB step size +12 dB (maximum volume) 7Fhex 7Ehex +11 dB ... 74hex +1 dB 73hex 0 dB -1 dB 72hex ... 02hex -113 dB 01hex -114 dB 00hex Mute (reset condition) higher resolution volume table 0 +0 dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table 01hex this must be 01hex VOL_SCART1 VOL_SCART2
bit[7:5]
bit[4:0]
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PRELIMINARY DATA SHEET
MSP 44x8G
Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
SCART SWITCHES AND DIGITAL I/O PINS 00 13hex ACB Register Defines the level of the digital output pins and the position of the SCART switches bit[15] bit[14] bit[13:5] 0/1 0/1 low/high of digital output pin D_CTR_I/O_0 (MODUS[3]=0) low/high of digital output pin D_CTR_I/O_1 (MODUS[3]=0) ACB_REG
SCART DSP Input Select xxxx00 xx0 SCART1 to DSP input (RESET position) xxxx01 xx0 MONO to DSP input (Sound A Mono must be selected in the channel matrix mode for the corresponding output channels) xxxx10 xx0 SCART2 to DSP input xxxx11 xx0 SCART3 to DSP input xxxx00 xx1 SCART4 to DSP input xxxx11 xx1 mute DSP input SCART1 Output Select xx00xx x0x SCART3 input to SCART1 output (RESET position) xx01xx x0x SCART2 input to SCART1 output xx10xx x0x MONO input to SCART1 output xx11xx x0x SCART1 DA to SCART1 output xx00xx x1x SCART2 DA to SCART1 output xx01xx x1x SCART1 input to SCART1 output xx10xx x1x SCART4 input to SCART1 output xx11xx x1x mute SCART1 output SCART2 Output Select 00xxxx 0xx SCART1 DA to SCART2 output (RESET position) 01xxxx 0xx SCART1 input to SCART2 output 10xxxx 0xx MONO input to SCART2 output 00xxxx 1xx SCART2 DA to SCART2 output 01xxxx 1xx SCART2 input to SCART2 output 10xxxx 1xx SCART3 input to SCART2 output 11xxxx 1xx SCART4 input to SCART2 output 11xxxx 0xx mute SCART2 output
bit[13:5]
bit[13:5]
The RESET position becomes active at the time of the first write transmission on the control bus to the audio processing part. By writing to the ACB register first, the RESET state can be redefined.
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Table 3-11: Write Registers on I2C Subaddress 12hex, continued Register Address Function
PRELIMINARY DATA SHEET
Name
MIXING UNIT 00 3Ahex 00 3Bhex MIX1 Scale MIX2 Scale Defines the input scale value for the digital mixing unit bit[15:8] 00hex 20hex 40hex 7Fhex off 50% (-6 dB gain) 100% (0 dB gain) 200% (+6 dB gain = maximum gain) VOL_MIX1 VOL_MIX2
Note: If the sum of both mixing inputs exceeds 100%, clipping may occur in the successive processing. BEEPER 00 14hex Beeper Volume and Frequency bit[15:8] Beeper Volume off 00hex maximum volume 7Fhex Beeper Frequency 16 Hz (lowest) 01hex 1 kHz 40hex 4 kHz FFhex BEEPER
bit[7:0]
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PRELIMINARY DATA SHEET
MSP 44x8G
3.3.2.6. Read Registers on I2C Subaddress 13hex Table 3-12: Read Registers on I2C Subaddress 13hex Register Address Function Name
QUASI-PEAK DETECTOR READOUT 00 19hex 00 1Ahex Quasi-Peak Detector Readout Left Quasi-Peak Detector Readout Right bit[15:0] 0hex... 7FFFhex values are 16 bit two's complement (only positive) QPEAK_L QPEAK_R
MSP 44x8G VERSION READOUT Registers 001Ehex MSP Hardware Version Code bit[15:8] 01hex MSP 44x8G-A1 MSP_HARD
A change in the hardware version code defines hardware optimizations that may have influence on the chip's behavior. The readout of this register is identical to the hardware version code in the chip's imprint. MSP Family Code bit[7:4] 1hex MSP 44x8G-A1 MSP_REVISION MSP_FAMILY
MSP Major Revision Code bit[3:0] 001Fhex 7hex MSP 44x8G-A1
MSP Product Code bit[15:8] 08hex 12hex 1Chex 30hex 3Ahex MSP 4408G-A1 MSP 4418G-A1 MSP 4428G-A1 MSP 4448G-A1 MSP 4458G-A1
MSP_PRODUCT
By means of the MSP-Product Code, the control processor is able to decide which TV sound standards have to be considered. MSP ROM Version Code bit[7:0] 41hex MSP 44x8G-A1 MSP_ROM
A change in the ROM version code defines internal software optimizations, that may have influence on the chip's behavior, e.g. new features may have been included. While a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new MSP 44x8G versions according to this number.
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3.4. Programming Tips This section describes the preferred method for initializing the MSP 44x8G. The initialization is grouped into four sections: - SCART Signal Path (analog signal path) - Demodulator Input - SCART and I2S Inputs - Output Channels See Fig. 2-1 on page 8 for a complete signal flow.
PRELIMINARY DATA SHEET
3.5. Examples of Minimum Initialization Codes Initialization of the MSP 44x8G according to these listings reproduces sound of the selected standard on the main output. All numbers are hexadecimal. The examples have the following structure: 1. Perform an I2C controlled reset of the IC. 2. Write MODUS register (with Automatic Sound Select). 3. Set Source Selection for main channel (with matrix set to STEREO). 4. Set Prescale (FM and/or NICAM and dummy FM matrix).
SCART Signal Path 1. Select analog input for the SCART baseband processing (SCART DSP Input Select) by means of the ACB register. 2. Select the source for each analog SCART output (SCART Output Select) by means of the ACB register.
5. Write STANDARD SELECT register. 6. Set Volume main channel to 0 dB.
3.5.1. B/G-FM (A2 or NICAM)
<80 00 80 00> <80 00 00 00> <80 10 00 30 20 03>
// MODUS-Register: Automatic = on // Source Sel. = (St or A) & Ch. Matr. = St // FM/AM-Prescale = 24hex, FM-Matrix = MONO/SOUNDA // NICAM-Prescale = 5Ahex // Standard Select: A2 B/G or NICAM B/G // Softreset
Demodulator Input For a complete setup of the sound processing from analog IF input to the source selection, the following steps must be performed: 1. Set MODUS register to the preferred mode and Sound IF input. 2. Write STANDARD SELECT register. 3. Choose preferred prescale (FM and NICAM) values. 4. If Automatic Sound Select is not active: Choose FM matrix repeatedly according to the sound mode indicated in the STATUS register. SCART and I2S Inputs 1. Select preferred prescale for SCART. 2. Select preferred prescale for I2S inputs (set to 0 dB after RESET).
<80 12 00 08 03 20> <80 12 00 0E 24 03> <80 12 00 10 00 5A> <80 10 00 20 00 03> or <80 10 00 20 00 08> <80 12 00 00 73 00>
// Main Volume 0 dB
3.5.2. BTSC-Stereo
<80 00 80 00> <80 00 00 00> <80 10 00 30 20 03> <80 12 00 08 03 20> <80 12 00 0E 24 03> <80 10 00 20 00 20> <80 12 00 00 73 00>
// MODUS-Register: Automatic = on // Source Sel. = (St or A) & Ch. Matr. = St // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono // Standard Select: BTSC-STEREO // Main Volume 0 dB // Softreset
3.5.3. BTSC-SAP with SAP at Main Channel
<80 00 80 00>
// Softreset // MODUS-Register: Automatic = on // Source Sel. = (St or B) & Ch. Matr. = St // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono // Standard Select: BTSC-SAP // Main Volume 0 dB
Output Channels 1. Select the source channel and matrix for each output channel. 2. Set audio baseband features (i.e. AVC, 75 s preemphasis) 3. Select volume for each output channel.
<80 00 00 00> <80 10 00 30 20 03> <80 12 00 08 04 20> <80 12 00 0E 24 03> <80 10 00 20 00 21> <80 12 00 00 73 00>
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PRELIMINARY DATA SHEET
MSP 44x8G
3.5.4. FM-Stereo Radio
<80 00 80 00> <80 00 00 00> <80 10 00 30 20 03> <80 12 00 08 03 20> <80 12 00 0E 24 03> <80 10 00 20 00 40> <80 12 00 00 73 00>
// MODUS-Register: Automatic = on // Source Sel. = (St or A) & Ch. Matr. = St // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono // Standard Select: FM-STEREO-RADIO // Main Volume 0 dB // Softreset
3.5.5. Automatic Standard Detection A detailed software flow diagram is shown in Fig. 3-2 on page 36.
<80 00 80 00> <80 00 00 00> <80 10 00 30 20 03> <80 12 00 08 03 20> <80 12 00 0E 24 03> <80 12 00 10 00 5A> <80 10 00 20 00 01>
// MODUS-Register: Automatic = on // Source Sel. = (St or A) & Ch. Matr. = St // FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono // NICAM-Prescale = 5Ahex // Standard Select: Automatic Standard Detection // Softreset
// Wait till STANDARD RESULT contains a value 07FF // IF STANDARD RESULT contains 0000 // do some error handling // ELSE
<80 12 00 00 73 00>
// Main Volume 0 dB
3.5.6. Software Flow for Interrupt driven STATUS Check A detailed software flow diagram is shown in Fig. 3-2 on page 36. If the D_CTR_I/O_1 pin of the MSP 44x8G is connected to an interrupt input pin of the controller, the following interrupt handler can be applied to be automatically called with each status change of the MSP 44x8G. The interrupt handler may adjust the display according to the new status information.
Interrupt Handler:
<80 11 02 00 <81 dd dd> // Read STATUS
// adjust display with given status information // Return from Interrupt
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PRELIMINARY DATA SHEET
Write MODUS Register:
Example for the essential bits: [0] = 1 Automatic Sound Select = on [1] = 1 Enable interrupt if STATUS changes [8] = 0 ANA_IN1+ is selected Define Preference for Automatic Standard Detection: [12] = 0 If 6.5 MHz, set SECAM-L [14:13] = 3 Ignore 4.5 MHz carrier
Write SOURCE SELECT Settings
Example: set main Source Select to "Stereo or A" set aux Source Select to "Stereo or B" set SCART_Out Source Select to "Stereo or A/B" set Channel Matrix mode for all outputs to "Stereo"
Write FM/AM-Prescale Write NICAM-Prescale
Write 01 into STANDARD SELECT Register
(Start Automatic Standard Detection)
set previous standard or set standard manually according picture information
yes
Result = 0 ?
no expecting interrupt from MSP
In case of interrupt from MSP to Controller:
Read STATUS
Adjust Display
If bilingual, adjust Source Select setting if required
Fig. 3-2: Software flow diagram for a minimum demodulator setup for a European multistandard set applying the Automatic Sound Select feature
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PRELIMINARY DATA SHEET
MSP 44x8G
4. Specifications 4.1. Outline Dimensions
23 x 0.8 = 18.4 0.1 0.8
0.17 0.04 64 65 1.8 10.3 9.8 16 8 0.37 0.05 14 0.1 41 40
17.2 0.15
1.8
8
5
80 1
25 1.3 0.05 2.7 0.1 3 0.2 0.1 20 0.1
24 23.2 0.15
SPGS705000-1(P80)/1E
Fig. 4-1: 80-Pin Plastic Quad Flat Pack (PQFP80) Weight approximately 1.61 g Dimensions in mm
15 x 0.5 = 7.5 0.1 0.145 0.055 48 49 12 0.2 33 15 x 0.5 = 7.5 0.1 32 10 0.1 0.5 0.5
1.75
64 1 1.75 12 0.2 16
17
1.4 0.05 1.5 0.1 0.1 10 0.1
0.22 0.05
D0025/3E
Fig. 4-2: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 0.35 g Dimensions in mm
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0.8
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MSP 44x8G
PRELIMINARY DATA SHEET
SPGS0016-5(P64)/1E
64
33
1
32
57.7 0.1
0.8 0.2 3.8 0.1
19.3 0.1 18 0.05
0.28 0.06 3.2 0.2 1 0.05 1.778 0.48 0.06 31 x 1.778 = 55.1 0.1 20.3 0.5
Fig. 4-3: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm
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PRELIMINARY DATA SHEET
MSP 44x8G
4.2. Pin Connections and Short Descriptions NC = not connected (leave vacant for future compatibility reasons) TP = Test Pin (leave vacant - pin is used for production test only) LV = leave vacant X = obligatory; connect as described in application circuit diagram
Pin No.
PQFP 80-pin PLQFP 64-pin PSDIP 64-pin
Pin Name
Type
Connection
(if not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25 26
64 1 2 3 4 5 6 7 8 9 - - 10 - - 11 12 - 13 14 15 16 - - 17 18 19
8 9 10 11 12 13 14 15 16 17 - - 18 - - 19 20 - 21 22 23 24 - - 25 26 27
NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSUP DVSUP DVSS DVSS DVSS I2S_DA_IN2/3 I2S_DA_IN2 NC I2S_CL3 I2S_WS3 RESETQ I2S_DA_IN3 NC DACA_R DACA_L VREF2 OUT OUT IN IN IN IN IN IN IN/OUT IN/OUT IN/OUT IN/OUT OUT IN OUT OUT OUT
LV X X LV LV LV LV LV LV LV X X X X X X LV LV LV LV LV X LV LV LV LV X
Not connected I2C clock I2C data I2S clock I2S word strobe I2S data output I2S1 data input ADR data output ADR word strobe ADR clock Digital power supply +5 V Digital power supply +5 V Digital power supply +5 V Digital ground Digital ground Digital ground I2S2/3-data input
PQFP80: pin 22 separate I2S_DA_IN3
Not connected I2S3 clock I2S3 word strobe Power-on-reset I2S3-data input Not connected Aux out, right Aux out, left Reference ground 2
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PRELIMINARY DATA SHEET
Pin No.
PQFP 80-pin PLQFP 64-pin PSDIP 64-pin
Pin Name
Type
Connection
(if not used)
Short Description
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
20 21 22 23 24 - 25 26 27 28 29 30 31 32 - - - 33 34 - 35 36 37 38 39 40 41 42 43 44 45
28 29 30 31 32 - 33 34 35 36 37 38 39 40 - - - 41 42 - 43 44 45 46 47 48 49 50 51 52 53
DACM_R DACM_L NC NC NC NC SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP CAPL_M NC NC AHVSS AHVSS AGNDC NC SC4_IN_L SC4_IN_R ASG SC3_IN_L SC3_IN_R ASG SC2_IN_L SC2_IN_R ASG SC1_IN_L SC1_IN_R
OUT OUT
LV LV LV LV LV LV
Main out, right Main out, left Not connected Not connected Not connected Not connected SCART output 2, right SCART output 2, left Reference ground 1 SCART output 1, right SCART output 1, left Volume capacitor Aux Analog power supply 8.0 V Volume capacitor Main Not connected Not connected Analog ground Analog ground Analog reference voltage Not connected SCART 4 input, left SCART 4 input, right Analog Shield Ground SCART 3 input, left SCART 3 input, right Analog Shield Ground SCART 2 input, left SCART 2 input, right Analog Shield Ground SCART 1 input, left SCART 1 input, right
OUT OUT
LV LV X
OUT OUT
LV LV X X X LV LV X X X LV
IN IN
LV LV AHVSS
IN IN
LV LV AHVSS
IN IN
LV LV AHVSS
IN IN
LV LV
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PRELIMINARY DATA SHEET
MSP 44x8G
Pin No.
PQFP 80-pin PLQFP 64-pin PSDIP 64-pin
Pin Name
Type
Connection
(if not used)
Short Description
58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
46 - 47 - 48 - - - 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
54 - 55 - 56 - - - 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7
VREFTOP NC MONO_IN AVSS AVSS NC NC AVSUP AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ IN/OUT IN/OUT IN IN OUT IN IN IN IN IN OUT IN
X LV LV X X LV LV X X LV AVSS via 56 pF / LV AVSS via 56 pF / LV AVSS X X / LV LV LV LV LV LV LV X X
Reference voltage IF A/D converter Not connected Mono input Analog ground Analog ground Not connected Not connected Analog power supply +5 V Analog power supply +5 V IF input 1 IF common (Can be left vacant, only if IF input 1 is also not in use) IF input 2 (Can be left vacant, only if IF input 1 is also not in use) Test pin Crystal oscillator Crystal oscillator (See also Section 4.3. "Pin Descriptions" on page 42) Test pin Audio clock output (18.432 MHz) Not connected Not connected D_CTR_I/O_1 D_CTR_I/O_0 I2C Bus address select Stand-by (low-active)
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4.3. Pin Descriptions Pin numbers refer to the 80-pin PQFP package. Pin 1, NC - Pin not connected. Pin 2, I2C_CL - I2C Clock Input/Output (Fig. 4-8) Via this pin, the I2C-bus clock signal has to be supplied. The signal can be pulled down by the MSP in case of wait conditions. Pin 3, I2C_DA - I2C Data Input/Output (Fig. 4-8) Via this pin, the I2C-bus data is written to or read from the MSP. Pin 4, I2S_CL - I2S Clock Input/Output (Fig. 4-11) Clock line for the synchronous I2S bus. In master mode, this line is driven by the MSP; in slave mode, an external I2S clock has to be supplied. Pin 5, I2S_WS - I2S Word Strobe Input/Output (Fig. 4-11) Word strobe line for the synchronous I2S bus. In master mode, this line is driven by the MSP; in slave mode, an external I2S word strobe has to be supplied. Pin 6, I2S_DA_OUT1 - I2S Data Output (Fig. 4-7) Output of digital serial sound data of the MSP on the synchronous I2S bus. Pin 7, I2S_DA_IN1 - I2S Data Input 1 (Fig. 4-9) First input of digital serial sound data to the MSP via the synchronous I2S bus. Pin 8, ADR_DA - ADR Bus Data Output (Fig. 4-7) Output of digital serial data to the DRP 3510A via the ADR bus. Pin 9, ADR_WS - ADR Bus Word Strobe Output (Fig. 4-7) Word strobe output for the ADR bus. Pin 10, ADR_CL - ADR Bus Clock Output (Fig. 4-7) Clock line for the ADR bus. Pins 11, 12, 13, DVSUP* - Digital Supply Voltage Power supply for the digital circuitry of the MSP. Must be connected to a +5 V power supply. Pins 14, 15, 16, DVSS* - Digital Ground Ground connection for the digital circuitry of the MSP. Pin 17, I2S_DA_IN2 - I2S Data Input 2 (Fig. 4-9) Second input of digital serial sound data to the MSP via the synchronous I2S bus. In all packages except PQFP80, this pin is also connected to the asynchronous I2S interface 3. Pins 18, NC - Pin not connected.
PRELIMINARY DATA SHEET
Pins 19, I2S_CL3 - I2S Clock Input (Fig. 4-9) Clock line for the asynchronous I2S bus. Since only a slave mode is available an external I2S clock has to be supplied. Pins 20, I2S_WS3 - I2S Word Strobe Input (Fig. 4-9) Word strobe line for the asynchronous I2S bus. Since only a slave mode is available an external I2S word strobe has to be supplied. Pin 21, RESETQ - Reset Input (Fig. 4-9) In the steady state, high level is required. A low level resets the MSP 44x8G. Pin 22, I2S_DA_IN3 - I2S Data Input 3 (Fig. 4-9) Input of digital serial sound data to the MSP via the asynchronous I2S bus. In all packages except PQFP80, this pin is also connected to synchronous I2S interface 2. Pins 23, NC - Pin not connected. Pins 24, 25, DACA_R/L - Aux Outputs (Fig. 4-17) Output of the Aux signal. A 1 nF capacitor to AHVSS must be connected to these pins. The DC offset on these pins depends on the selected Aux volume. Pin 26, VREF2 - Reference Ground 2 Reference analog ground. This pin must be connected separately to the ground (AHVSS). VREF2 serves as a clean ground and should be used as the reference for analog connections to the Main and Aux outputs. Pins 27, 28, DACM_R/L - Main Outputs (Fig. 4-17) Output of the Main signal. A 1 nF capacitor to AHVSS must be connected to these pins. The DC offset on these pins depends on the selected Main volume. Pin 29, 30, 31, 32 NC - Pin not connected. Pins 33, 34, SC2_OUT_R/L - SCART2 Outputs (Fig. 4-19) Output of the SCART2 signal. Connections to these pins must use a 100- series resistor and are intended to be AC-coupled. Pin 35, VREF1 - Reference Ground 1 Reference analog ground. This pin must be connected separately to the ground (AHVSS). VREF1 serves as a clean ground and should be used as the reference for analog connections to the SCART outputs. Pins 36, 37, SC1_OUT_R/L - SCART1 Outputs (Fig. 4-19) Output of the SCART1 signal. Connections to these pins must use a 100- series resistor and are intended to be AC-coupled.
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PRELIMINARY DATA SHEET
MSP 44x8G
Pins 56, 57 SC1_IN_L/R - SCART1 Inputs (Fig. 4-16) The analog input signal for SCART1 is fed to this pin. Analog input connection must be AC-coupled. Pin 58, VREFTOP - Reference Voltage IF A/D Converter (Fig. 4-13) Via this pin, the reference voltage for the IF A/D converter is decoupled. It must be connected to AVSS pins with a 10-F and a 100-nF capacitor in parallel. Traces must be kept short. Pin 59, NC - Pin not connected. Pin 60 MONO_IN - Mono Input (Fig. 4-16) The analog mono input signal is fed to this pin. Analog input connection must be AC-coupled. Pins 61, 62, AVSS* - Analog Power Supply Voltage Ground connection for the analog IF input circuitry of the MSP. Pins 63, 64, NC - Pins not connected. Pins 65, 66, AVSUP* - Analog Power Supply Voltage Power is supplied via this pin for the analog IF input circuitry of the MSP. This pin must be connected to the +5 V supply. Pin 67, ANA_IN1+ - IF Input 1 (Fig. 4-13) The analog sound IF signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN1+ is internally connected to one input of a symmetrical op amp, ANA_IN- to the other. Pin 68, ANA_IN- - IF Common (Fig. 4-13) This pins serves as a common reference for ANA_IN1/ 2+ inputs and must be AC-coupled. Pin 69, ANA_IN2+ - IF Input 2 (Fig. 4-13) The analog sound if signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN2+ is internally connected to one input of a symmetrical op amp, ANA_IN- to the other. Pin 70, TESTEN - Test Enable Pin (Fig. 4-9) This pin enables factory test modes. For normal operation, it must be connected to ground.
Pin 38, CAPLA - Volume Capacitor Aux (Fig. 4-14) A 10-F capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for Aux volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1-F if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induction. Pin 39, AHVSUP* - Analog Power Supply High Voltage Power is supplied via this pin for the analog circuitry of the MSP (except IF input). This pin must be connected to the +8 V supply. (+5 V-operation is possible with restrictions in performance) Pin 40, CAPLM - Volume Capacitor Main (Fig. 4-14) A 10-F capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for Main volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1 F if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induction. Pins 41, 42, NC - Pins not connected. Pins 43, 44, AHVSS* - Analog Power Supply High Voltage Ground connection for the analog circuitry of the MSP (except IF input). Pin 45, AGNDC - Internal Analog Reference Voltage This pin serves as the internal ground connection for the analog circuitry (except IF input). It must be connected to the VREF pins with a 3.3-F and a 100-nF capacitor in parallel. This pins shows a DC level of typically 3.73 V. Pin 46, NC - Pin not connected. Pins 47, 48, SC4_IN_L/R - SCART4 Inputs (Fig. 4-16) The analog input signal for SCART4 is fed to this pin. Analog input connection must be AC-coupled. Pins 49, 52, and 55, ASG* - Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 50, 51, SC3_IN_L/R - SCART3 Inputs (Fig. 4-16) The analog input signal for SCART3 is fed to this pin. Analog input connection must be AC-coupled. Pins 53, 54 SC2_IN_L/R - SCART2 Inputs (Fig. 4-16) The analog input signal for SCART2 is fed to this pin. Analog input connection must be AC-coupled.
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Pins 71, 72 XTAL_IN, XTAL_OUT - Crystal Input and Output Pins (Fig. 4-12) These pins are connected to an 18.432 MHz crystal oscillator which is digitally tuned by integrated capacitances. An external clock can be fed into XTAL_IN (leave XTAL_OUT vacant in this case). The audio clock output signal AUD_CL_OUT is derived from the oscillator. External capacitors at each crystal pin to ground (AVSS) are required. It should be verified by layout, that no supply current for the digital circuitry is flowing through the ground connection point. Pin 73, TP - This pin enables factory test modes. For normal operation, it must be left vacant. Pin 74, AUD_CL_OUT - Audio Clock Output (Fig. 4-12) This is the 18.432 MHz main clock output. Pins 75, 76, NC - Pins not connected. Pins 77, 78, D_CTR_I/O_1/0 - Digital Control Input/ Output Pins (Fig. 4-11) These pins serve as general purpose input/output pins. Pin D_CTR_I/O_1 can be used as an interrupt request pin to the controller. Pin 79, ADR_SEL - I2C Bus Address Select (Fig. 4-10) By means of this pin, one of three device addresses for the MSP can be selected. The pin can be connected to ground (I2C device addresses 80/81hex), to +5 V supply (84/85hex), or left open (88/89hex). Pin 80, STANDBYQ - Stand-by In normal operation, this pin must be High. If the MSP is switched off by first pulling STANDBYQ low and then (after >1 s delay) switching off the 5 V, but keeping the 8-V power supply (`Stand-by'-mode), the SCART switches maintain their position and function. Pin -, I2S_DA_IN2/3 -I2S data input (see Fig. 4-9). This pin is connected to I2S_DA_IN2 and I2S_DA_IN3. Not available for PQFP80-pin package.
PRELIMINARY DATA SHEET
* Application Note: All ground pins should be connected to one low-resistive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are recommended as closely as possible to these pins. Decoupling of DVSUP and DVSS is most important. We recommend using more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended. In our application boards we use: 220 pF, 470 pF, 1.5 nF, and 10 F. The capacitor with the lowest value should be placed nearest to the pins. The ASG pins should be connected as closely as possible to the MSP ground. They are intended for leading with the SCART signals as shield lines and should not be connected to ground at the SCART-connector.
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PRELIMINARY DATA SHEET
MSP 44x8G
4.4. Pin Configurations
SC2_IN_L SC2_IN_R ASG SC1_IN_L SC1_IN_R VREFTOP NC MONO_IN AVSS AVSS NC NC
ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L NC AGNDC AHVSS AHVSS NC NC
AVSUP AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 40 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 39 38 37 36 35 34
CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC NC NC NC DACM_L DACM_R VREF2 DACA_L
MSP 44x8G
33 32 31 30 29 28 27 26
25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSUP NC I2S_DA_IN2 DVSS DVSS DVSS DVSUP NC
DACA_R
I2S_DA_IN3 RESETQ I2S_WS3 I2S_CL3
Fig. 4-4: 80-pin PQFP package
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MSP 44x8G
PRELIMINARY DATA SHEET
SC2_IN_L SC2_IN_R ASG SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS
ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L AGNDC AHVSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_I/O_1 C_CTR_I/O_0 ADR_SEL STANDBYQ NC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS NC I2S_DA_IN2/3 DVSS DVSUP ADR_CL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RESETQ I2S_WS3 I2S_CL3 32 31 30 29 28 27 26 CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC NC NC DACM_L DACM_R VREF2 DACA_L DACA_R
MSP 44x8G
25 24 23 22 21 20 19 18 17
Fig. 4-5: 64-pin PLQFP package
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PRELIMINARY DATA SHEET
MSP 44x8G
AUD_CL_OUT NC NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2S_DA_IN2/3 NC I2S_CL3 I2S_WS3 RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52
TP XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG SC2_IN_R SC2_IN_L ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
MSP 44x8G
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Fig. 4-6: 64-pin PSDIP package
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MSP 44x8G
4.5. Pin Circuits Pin numbers refer to the PQFP80 package. DVSUP P N GND Fig. 4-7: Output Pins 6, 8, 9, and 10 (I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL) P N GND DVSUP
PRELIMINARY DATA SHEET
Fig. 4-11: Input/Output Pins 4, 5, 77, and 78 (I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0)
P N GND Fig. 4-8: Input/Output Pins 2 and 3 (I2C_CL, I2C_DA)
3-30 pF 500 k Gain=0.5
N
2.5 V
3-30 pF
Fig. 4-12: Output/Input Pins 71, 72, and 74 (XTAL_IN, XTAL_OUT, AUD_CL_OUT) Fig. 4-9: Input Pins 7, 17, 22, 19, 20, 21, 70, and 80 (I2S_DA_IN1..3, I2S_CL3, I2S_WS3, RESETQ, TESTEN, STANDBYQ) ANA_IN1+ ANA_IN2+ DVSUP
23 k
A D
ANA_IN- VREFTOP
23 k
GND ADR_SEL Fig. 4-10: Input Pin 79 (ADR_SEL) Fig. 4-13: Input Pins 58, 67, 68, and 69 (VREFTOP, ANA_IN1+, ANA_IN-, ANA_IN2+)
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PRELIMINARY DATA SHEET
MSP 44x8G
125 k 0...2 V 3.75 V
Fig. 4-14: Capacitor Pins 38 and 40 (CAPL_A, CAPL_M)
Fig. 4-18: Pin 45 (AGNDC)
26 pF 24 k 3.75 V 120 k
Fig. 4-15: Input Pin 60 (MONO_IN)
3.75 V
300
40 k 3.75 V
Fig. 4-19: Output Pins 33, 34, 36, and 37 (SC_2_OUT_R/L, SC_1_OUT_R/L)
Fig. 4-16: Input Pins 47, 48, 50, 51, 53, 54, 56, and 57 (SC4-1_IN_L/R)
AHVSUP
0...1.2 mA
3.3 k
Fig. 4-17: Output Pins 24, 25, 27, and 28 (DACA_R/L, DACM_R/L)
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4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol TA TS VSUP1 VSUP2 VSUP3 dVSUP23 PTOT Parameter Ambient Operating Temperature Storage Temperature First Supply Voltage Second Supply Voltage Third Supply Voltage Voltage between AVSUP and DVSUP Package Power Dissipation PSDIP64 PLQFP64 PQFP80 Input Voltage, all Digital Inputs Input Current, all Digital Pins Input Voltage, all Analog Inputs Input Current, all Analog Inputs Output Current, all SCART Outputs Output Current, all Analog Outputs except SCART Outputs Output Current, other pins connected to capacitors SCn_IN_s,3) MONO_IN SCn_IN_s,3) MONO_IN SCn_OUT_s3) DACp_s3) CAPL_p,3) AGNDC Pin Name - - AHVSUP DVSUP AVSUP AVSUP, DVSUP AHVSUP, DVSUP, AVSUP -0.3 -20 -0.3 -5
4), 5) 4)
PRELIMINARY DATA SHEET
Min. 0 -40 -0.3 -0.3 -0.3 -0.5
Max. 701) 125 9.0 6.0 6.0 0.5
Unit C C V V V V
1300 960 1000 VSUP2+0.3 +20 VSUP1+0.3 +5
4), 5) 4)
mW mW mW V mA2) V mA2)
VIdig IIdig VIana IIana IOana IOana ICana
1) 2) 3) 4) 5)
4)
4)
PLQFP64: 65 C positive value means current flowing into the circuit "n" means "1", "2", "3", or "4", "s" means "L" or "R", "p" means "M" or "A" The Analog Outputs are short-circuit proof with respect to First Supply Voltage and Ground. Total chip power dissipation must not exceed absolute maximum rating.
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
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PRELIMINARY DATA SHEET
MSP 44x8G
4.6.2. Recommended Operating Conditions (TA = 0 to 70 C) 4.6.2.1. General Recommended Operating Conditions Symbol VSUP1 Parameter First Supply Voltage (8-V Operation) First Supply Voltage (5-V Operation) VSUP2 Second Supply Voltage (5-V Operation) Second Supply Voltage (3.3-V Operation) VSUP3 tSTBYQ1 Third Supply Voltage STANDBYQ Setup Time before Turn-off of Second Supply Voltage AVSUP STANDBYQ, DVSUP DVSUP Pin Name AHVSUP Min. 7.6 4.75 4.75 3.15 4.75 1 Typ. 8.0 5.0 5.0 3.3 5.0 Max. 8.7 5.25 5.25 3.45 5.25 Unit V V V V V s
4.6.2.2. Analog Input and Output Recommendations Symbol CAGNDC Parameter AGNDC-Filter-Capacitor Ceramic Capacitor in Parallel CinSC VinSC VinMONO RLSC CLSC CVMA CFMA
1)
Pin Name AGNDC
Min. -20% -20%
Typ. 3.3 100 330
Max.
Unit F nF nF
DC-Decoupling Capacitor in front of SCART Inputs SCART Input Level Input Level, Mono Input SCART Load Resistance SCART Load Capacitance Main/Aux Volume Capacitor Main/Aux Filter Capacitor
SCn_IN_s1)
-20%
2.0 MONO_IN SCn_OUT_s1) 10 6.0 CAPL_M, CAPL_A DACM_s, DACA_s1) -10% 10 1 +10% 2.0
VRMS VRMS k nF F nF
"n" means "1", "2", or "3", "s" means "L" or "R", "p" means "M" or "A"
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4.6.2.3. Recommendations for Analog Sound IF Input Signal Symbol CVREFTOP Parameter VREFTOP-Filter-Capacitor Ceramic Capacitor in Parallel FIF_FMTV FIF_FMRADIO VIF_FM VIF_AM RFMNI Analog Input Frequency Range for TV Applications Analog Input Frequency for FM-Radio Applications Analog Input Range FM/NICAM Analog Input Range AM/NICAM Ratio: NICAM Carrier/FM Carrier (unmodulated carriers) BG: I: Ratio: NICAM Carrier/AM Carrier (unmodulated carriers) Ratio: FM-Main/FM-Sub Satellite Ratio: FM1/FM2 German FM-System Ratio: Main FM Carrier/ Color Carrier Ratio: Main FM Carrier/ Luma Components Passband Ripple Suppression of Spectrum above 9.0 MHz (not for FM Radio) Maximum FM-Deviation (approx.) normal mode HDEV2: high deviation mode HDEV3: very high deviation mode 15 15 - 15 0.1 0.1 ANA_IN1+, ANA_IN2+, ANA_IN- Pin Name VREFTOP Min. -20 % -20 % 0
PRELIMINARY DATA SHEET
Typ. 10 100
Max.
Unit F nF
9 10.7 0.8 0.45 3 0.8
MHz MHz Vpp Vpp
-20 -23 -25
-7 -10 -11 7 7 - - -
0 0 0
dB dB dB dB dB
RAMNI RFM RFM1/FM2 RFC RFV PRIF SUPHF FMMAX
- - 2
dB dB dB dB
180 360 540
kHz kHz kHz
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PRELIMINARY DATA SHEET
MSP 44x8G
4.6.2.4. Crystal Recommendations Symbol Parameter Pin Name Min. Typ. Max. Unit
General Crystal Recommendations fP RR C0 CL Crystal Parallel Resonance Frequency at 12 pF Load Capacitance Crystal Series Resistance Crystal Shunt (Parallel) Capacitance External Load Capacitance1) XTAL_IN, XTAL_OUT 18.432 8 6.2 25 7.0 MHz pF pF pF
PSDIP approx. 1.5 P(L)QFP approx. 3.3
Crystal Recommendations for Master-Slave Applications (MSP-clock must perform synchronization to I2S clock) fTOL DTEM C1 fCL Accuracy of Adjustment Frequency Variation versus Temperature Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb = 25 C) AUD_CL_OUT -20 -20 19 18.431 24 18.433 +20 +20 ppm ppm fF MHz
Crystal Recommendations for FM / NICAM Applications (No MSP-clock synchronization to I2S clock possible) fTOL DTEM C1 fCL Accuracy of Adjustment Frequency Variation versus Temperature Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb = 25 C) AUD_CL_OUT -30 -30 15
18.4305 18.4335
+30 +30
ppm ppm fF MHz
Crystal Recommendations for all analog FM/AM Applications (No MSP-clock synchronization to I2S clock possible) fTOL DTEM fCL Accuracy of Adjustment Frequency Variation versus Temperature Required Open Loop Clock Frequency (Tamb = 25 C) AUD_CL_OUT -100 -50 18.429 +100 +50 18.435 ppm ppm MHz
Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF) VXCA
1)
External Clock Amplitude
XTAL_IN
0.7
Vpp
External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop frequency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the accurate capacitor size should be determined with the customer PCB. The suggested values (1.5...3.3 pF) are figures based on experience and should serve as "start value". To define the capacitor size, reset the MSP without transmitting any further I2C telegrams. Measure the frequency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz as closely as possible. The higher the capacity, the lower the resulting clock frequency.
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4.6.3. Characteristics
PRELIMINARY DATA SHEET
at TA = 0 to 70 C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.7 V, VSUP2 = 4.75 to 5.25 V for min./max. values at TA = 60 C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values, TJ = Junction Temperature Main (M) = Main Channel, Aux (A) = Aux Channel
4.6.3.1. General Characteristics
Symbol Supply ISUP1A First Supply Current (active) (8-V Operation)
Analog Volume for Main and Aux at 0 dB Analog Volume for Main and Aux at -30 dB
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
AHVSUP 18 12 25 17 mA mA
First Supply Current (active) (5-V Operation)
Analog Volume for Main and Aux at 0 dB Analog Volume for Main and Aux at -30 dB
12 8 DVSUP 70 60 AVSUP AHVSUP 35 5.6
17 11 85 75 45 7.7
mA mA mA mA mA mA STANDBYQ = low
ISUP2A
Second Supply Current (active) (5-V Operation) Second Supply Current (active) (3.3-V Operation)
ISUP3A ISUP1S
Third Supply Current (active) First Supply Current (8-V Operation) (standby mode) at Tj = 27 C First Supply Current (5-V Operation) (standby mode) at Tj = 27 C
3.7
5.1
mA
STANDBYQ = low
Clock fCLOCK DCLOCK tJITTER VxtalDC tStartup VACLKAC VACLKDC routHF_ACL Clock Input Frequency Clock High to Low Ratio Clock Jitter (Verification not provided in Production Test) DC-Voltage Oscillator Oscillator Startup Time at VDD Slew-rate of 1 V/s Audio Clock Output AC Voltage Audio Clock Output DC Voltage HF Output Resistance XTAL_IN, XTAL_OUT AUD_CL_OUT 1.2 0.4 140 2.5 0.4 1.8 0.6 2 XTAL_IN 45 18.432 55 50 MHz % ps V ms Vpp VSUP3 load = 40 pF Imax = 0.2 mA
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PRELIMINARY DATA SHEET
MSP 44x8G
4.6.3.2. Digital Inputs, Digital Outputs
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Digital Inputs Levels VDIGIL VDIGIH ZDIGI IDLEAK VDIGIL VDIGIH IADRSEL Digital Input Low Voltage Digital Input High Voltage Input Impedance Digital Input Leakage Current ADR_SEL Input Low Voltage ADR_SEL Input High Voltage Input Current ADR_SEL 0.8 -500 -220 220 Digital Output Levels VDCTROL VDCTROH Digital Output Low Voltage Digital Output High Voltage D_CTR_I/O_0 D_CTR_I/O_1 VSUP2 - 0.3 0.4 V V IDDCTR = 1 mA IDDCTR = -1 mA 500 -1 STANDBYQ D_CTR_I/O_0/1 0.5 5 1 0.2 0.2 VSUP2 VSUP2 pF A VSUP2 VSUP2 A A UADR_SEL= DVSS UADR_SEL= DVSUP 0 V < UINPUT< DVSUP D_CTR_I/O_0/1: tri-state
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4.6.3.3. Reset Input and Power-Up
Symbol Parameter Pin Name Min. Typ. Max.
PRELIMINARY DATA SHEET
Unit
Test Conditions
RESETQ Input Levels VRHL VRLH ZRES IRES Reset High-Low Transition Voltage Reset Low-High Transition Voltage Input Impedance Input Pin Leakage Current -1 RESETQ 0.45 0.7 0.55 0.8 5 1 VSUP2 VSUP2 pF A 0 V < UINPUT< DVSUP
DVSUP AVSUP
VSUP2 - 10%
t/ms
RESETQ
0.7xVSUP2 0.45...0.55xVSUP2
Low-to-High Threshold
Note: The reset should not reach high level before the oscillator has started. This requires a reset delay of >2 ms
High-to-Low Threshold
0.7 x VSUP2 means 3.5 Volt with VSUP2 = 5.0 V t/ms
Reset Delay >2 ms
Internal Reset
High
Low
t/ms Fig. 4-20: Power-up sequence
56
Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
4.6.3.4. I2C-Bus Characteristics
Symbol VI2CIL VI2CIH tI2C1 tI2C2 tI2C5 tI2C6 tI2C3 tI2C4 fI2C VI2COL II2COH tI2COL1 tI2COL2 Parameter I C-BUS Input Low Voltage I2C-BUS Input High Voltage I2C START Condition Setup Time I C STOP Condition Setup Time I2C-Data Setup Time before Rising Edge of Clock I2C-Data Hold Time after Falling Edge of Clock I2C-Clock Low Pulse Time I2C-Clock High Pulse Time I2C_CL
2 2
Pin Name I2C_CL, I2C_DA
Min.
Typ.
Max. 0.3
Unit VSUP2 VSUP2 ns ns ns ns ns ns
Test Conditions
0.6 120 120 55 55 500 500 1.0 I2C_CL, I2C_DA 0.4 1.0 15 100
I2C-BUS Frequency I C-Data Output Low Voltage I C-Data Output High Leakage Current I2C-Data Output Hold Time after Falling Edge of Clock I2C-Data Output Setup Time before Rising Edge of Clock
2 2
MHz V A ns ns fI2C = 1 MHz II2COL = 3 mA VI2COH = 5 V
1/FI2C I2C_CL TI2C4 TI2C3
TI2C1 I2C_DA as input
TI2C5
TI2C6
TI2C2
TI2COL2 I2C_DA as output
TI2COL1
Fig. 4-21: I2C bus timing diagram
Micronas
57
MSP 44x8G
4.6.3.5. I2S-Bus Characteristics
Symbol VI2SIL VI2SIH ZI2SI ILEAKI2S VI2SOL VI2SOH fI2SOWS fI2SOCL RI2S10/I2S20 Parameter Input Low Voltage Input High Voltage Input Impedance Input Leakage Current I2S Output Low Voltage I S Output High Voltage I2S-Word Strobe Output Frequency I2S-Clock Output Frequency
2
PRELIMINARY DATA SHEET
Pin Name I2S_CL I2S_WS I2S_CL3 I2S_WS3 I2S_DA_IN1..3
Min.
Typ.
Max. 0.2
Unit VSUP2 VSUP2
Test Conditions
0.5 5 -1 1 0.4 VSUP2 - 0.3 48.0 1.536 0.9 1.0 1.1
pF A V V kHz MHz 0 V < UINPUT< DVSUP II2SOL = 1 mA II2SOH = -1 mA
I2S_CL I2S_WS I2S_DA_OUT I2S_WS I2S_CL
I2S-Clock Output High/Low-Ratio
Synchronous I2S Interface ts_I2S I2S Input Setup Time before Rising Edge of Clock I2S Input Hold Time after Rising Edge of Clock I2S Output Delay Time after Falling Edge of Clock I2S-Word Strobe Input Frequency I2S-Clock Input Frequency I S-Clock Input Ratio
2
I2S_DA_IN1/2 I2S_CL
12
ns
for details see Fig. 4-22 "I2S timing diagram (synchronous interface)"
th_I2S td_I2S
40 I2S_CL I2S_WS I2S_DA_OUT I2S_WS I2S_CL 0.9 48.0 1.536 1.1 28
ns ns CL=30 pF
fI2SWS fI2SCL RI2SCL
kHz MHz
Asynchronous I2S Interface ts_I2S3 th_I2S3 fI2S3WS fI2S3CL RI2S3CL I2S3 Input Setup Time before Rising Edge of Clock I2S3 Input Hold Time after Rising Edge of Clock I2S3-Word Strobe Input Frequency I2S3-Clock Input Frequency I S3-Clock Input Ratio
2
I2S_CL3 I2S_WS3 I2S_DA_IN3
4 40
ns ns 50 3.2 kHz MHz
for details see Fig. 4-23 "I2S timing diagram (asynchronous interface)"
I2S_WS3 I2S_CL3
5
0.9
1.1
58
Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
1/FI2SWS I2S_WS
MODUS[6] = 0 MODUS[6] = 1
Detail C
I2S_CL Detail A I2S_DA_IN*)
R LSB L MSB L LSB R MSB R LSB L LSB
16/32 bit left channel Detail B I2S_DA_OUT R LSB
L MSB L LSB R MSB
16/32 bit right channel
R LSB L LSB
16/32 bit left channel
16/32 bit right channel
Data: MSB first, I2S synchronous master
1/FI2SWS I2S_WS
MODUS[6] = 0 MODUS[6] = 1
Detail C
I2S_CL Detail A I2S_DA_IN*)
R LSB L MSB L LSB R MSB R LSB L LSB
16,18...32 bit left channel Detail B I2S_DA_OUT R LSB
L MSB
16, 18...32 bit right channel
16, 18...32 bit left channel
L LSB R MSB R LSB L LSB
16, 18...32 bit right channel
Data: MSB first, I2S synchronous slave
Note:
1) I2S_DA_IN can be - I2S_DA_IN1, - I2S_DA_IN2, or - I2S_DA_IN2/3
Detail C
I2S_CL
1/FI2SCL
Detail A,B
I2S_CL
Ts_I2S Ts_I2S I2S_DA_IN1) I2S_WS as INPUT
Th_I2S
Td_I2S
Td_I2S
I2S_WS as OUTPUT
I2S_DA_OUT
Fig. 4-22: I2S timing diagram (synchronous interface)
Micronas
59
MSP 44x8G
PRELIMINARY DATA SHEET
I2S_CL3 1/FI2S3WS
Left sample (I2S_CONFIG[10]
2
= 0)
Right sample (I2S_CONFIG[10] = 0) Right sample (I2S_CONFIG[10] = 1) Left aligned (I2S_CONFIG[9] = 0)
I2S_WS3
Left sample (I S_CONFIG[10] = 1)
I2S_DA_IN3
MSB
16,18...32 Bit data & clocks allowed Left aligned (I2S_CONFIG[9] = 1) 16,18...32 Bit data & clocks allowed
MSB
I2S_DA_IN3
MSB
MSB Right aligned (I2S_CONFIG[11] = 1, I2S_CONFIG[9] = 0) 16 Bit data & 16...32 clocks allowed
I2S_DA_IN3
LSB
LSB
1/FI2S3CL I2S_CL3
Ts_I2S3 Th_I2S3
I2S_DA_IN3 Ts_I2S3
I2S_WS3
Fig. 4-23: I2S timing diagram (asynchronous interface)
4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Analog Ground VAGNDC0 AGNDC Open Circuit Voltage 8-V Operation: 5-V Operation: RoutAGN AGNDC Output Resistance 8-V Operation: 5-V Operation: Analog Input Resistance RinSC RinMONO
1)
AGNDC 3.77 2.49 V V
Rload 10 M
3 V VAGNDC 4 V 70 47 125 83 180 120 k k
SCART Input Resistance from TA = 0 to 70 C MONO Input Resistance from TA = 0 to 70 C
SCn_IN_s1) MONO_IN
25 15
40 24
58 35
k k
fsignal = 1 kHz, I = 0.05 mA fsignal = 1 kHz, I = 0.1 mA
"n" means "1", "2", "3", or "4";
"s" means "L" or "R"
60
Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Audio Analog-to-Digital-Converter VAICL Effective Analog Input Clipping Level for Analog-to-DigitalConversion (8-V Operation) Effective Analog Input Clipping Level for Analog-to-DigitalConversion (5-V Operation) SCART Outputs RoutSC SCART Output Resistance at Tj = 27 C from TA = 0 to 70 C Deviation of DC-Level at SCART Output from AGNDC Voltage Gain from Analog Input to SCART Output Frequency Response from Analog Input to SCART Output (0 to 20000 Hz) Effective Signal Level at SCART-Output during full-scale Digital Input Signal from I2S (8-V Operation) Effective Signal Level at SCART-Output during full-scale Digital Input Signal from I2S (5-V Operation) Main and Aux Outputs RoutMA Main/Aux Output Resistance at Tj = 27 C from TA = 0 to 70 C DC-Level at Main/Aux-Output for Analog Volume at 0 dB for Analog Volume at -30 dB (8-V Operation) DC-Level at Main/Aux-Output for Analog Volume at 0 dB for Analog Volume at -30 dB (5-V Operation) VoutMA Effective Signal Level at Main/ Aux-Output during full-scale Digital Input Signal from I2S for Analog Volume at 0 dB (8-V Operation) Effective Signal Level at Main/ Aux-Output during full-scale Digital Input Signal from I2S for Analog Volume at 0 dB (5-V Operation)
1)
SCn_IN_s,1) MONO_IN
2.00
2.25
VRMS
fsignal = 1 kHz
1.13
1.51
VRMS
SCn_OUT_s1) 200 200 -70 SCn_IN_s,1) MONO_IN SCn_OUT_s1) -1.0 -0.5 330 460 500 +70 +0.5 +0.5
mV dB dB
fsignal = 1 kHz, I = 0.1 mA
dVOUTSC ASCtoSC frSCtoSC
fsignal = 1 kHz with resp. to 1 kHz
VoutSC
SCn_OUT_s1)
1.8
1.9
2.0
VRMS
fsignal = 1 kHz
1.17
1.27
1.37
VRMS
DACp_s1) 2.1 2.1 1.80 3.3 4.6 5.0 2.28 k k V mV
fsignal = 1 kHz, I = 0.1 mA
VoutDCMA
2.04 61
1.12
1.36 40 1.37
1.60
V mV VRMS fsignal = 1 kHz
1.23
1.51
0.76
0.90
1.04
VRMS
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
"p" means "M" or "A"
Micronas
61
MSP 44x8G
4.6.3.7. Sound IF Inputs
Symbol RIFIN DCVREFTOP DCANA_IN XTALKIF BWIF AGC Parameter Input Impedance DC Voltage at VREFTOP DC Voltage on IF Inputs Crosstalk Attenuation 3 dB Bandwidth AGC Step Width Pin Name ANA_IN1+ ANA_IN2+ ANA_IN- Min. 1.5 6.8 2.45 1.3 40 10 0.85 Typ. 2 9.1 2.65 1.5 Max. 2.5 11.4 2.75 1.7
PRELIMINARY DATA SHEET
Unit k k V V dB MHz dB
Test Conditions Gain AGC = 20 dB Gain AGC = 3 dB
fsignal = 1 MHz Input Level = -2 dBr
4.6.3.8. Power Supply Rejection
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
PSRR: Rejection of Noise on AHVSUP at 1 kHz PSRR AGNDC From Analog Input to I2S Output From Analog Input to SCART Output From I2S Input to SCART Output From I2S Input to Main/Aux Output
1)
AGNDC MONO_IN, SCn_IN_s1) MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1) "p" means "M" or "A"
80 70 70
dB dB dB
60 80
dB dB
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
62
Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
4.6.3.9. Analog Performance
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Specifications for 8-V Operation SNR Signal-to-Noise Ratio from Analog Input to I2S Output MONO_IN, SCn_IN_s1) 90 93 dB Input Level = -20 dB with resp. to VAICL, fsig = 1 kHz, A-weighted 20 Hz...20 kHz Input Level = -20 dB, fsig = 1 kHz, A-weighted 20 Hz...20 kHz Volume = 0 dB
from Analog Input to SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1)
93
96
dB
from I2S Input to SCART Output from THD I2S Input to Main/Aux-Output
90 90
93 93
dB dB
Total Harmonic Distortion from Analog Input to I2S Output MONO_IN, SCn_IN_s1) 0.01 0.03 % Input Level = -3 dBr with resp. to VAICL, fsig = 1 kHz, unweighted 20 Hz...20 kHz Input Level = -3 dBr, fsig = 1 kHz, unweighted 20 Hz...20 kHz
from Analog Input to SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1) DACA_s, DACM_s1) "p" means "M" or "A"
0.01
0.03
%
from I2S Input to SCART Output from I2S Input to Main or Aux Output
1)
0.01 0.01
0.03 0.03
% %
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
Micronas
63
MSP 44x8G
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Specifications for 5-V Operation SNR Signal-to-Noise Ratio from Analog Input to I2S Output MONO_IN, SCn_IN_s1) 87 90 dB Input Level = -20 dB with resp. to VAICL, fsig = 1 kHz, A-weighted 20 Hz...20 kHz Input Level = -20 dB, fsig = 1 kHz, A-weighted 20 Hz...20 kHz Volume = 0 dB
from Analog Input to SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1)
90
93
dB
from I2S Input to SCART Output from I2S Input to Main/Aux-Output for Analog Volume at 0 dB for Analog Volume at -30 dB THD Total Harmonic Distortion from Analog Input to I2S Output
87 87 75
90 90 80
dB dB dB
MONO_IN, SCn_IN_s1)
0.03
0.1
%
Input Level = -3 dBr with resp. to VAICL, fsig = 1 kHz, unweighted 20 Hz...20 kHz Input Level = -3 dBr, fsig = 1 kHz, unweighted 20 Hz...20 kHz
from Analog Input to SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1) DACA_s, DACM_s1) "p" means "M" or "A"
0.1
%
from I2S Input to SCART Output from I2S Input to Main or Aux Output
1)
0.1 0.1
% %
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
64
Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
Crosstalk Specifications for 8-V and 5-V Operation XTALK Crosstalk Attenuation Input Level = -3 dB, fsig = 1 kHz, unused analog inputs connected to ground by Z < 1 k unweighted 20 Hz...20 kHz 80 80 80 80 dB dB dB dB unweighted 20 Hz...20 kHz 75 dB (unweighted 20 Hz...20 kHz) same signal source on left and right disturbing channel, effect on each observed output channel
between left and right channel within SCART Input/Output pair (LR, RL) SCn_IN SCn_OUT1) SC1_IN or SC2_IN I2S Output SC3_IN I S Output
2
I2S Input SCn_OUT1) between left and right channel within Main or Aux Output pair I2S Input DACp1) between SCART Input/Output pairs1) D = disturbing program O = observed program D: MONO/SCn_IN SCn_OUT O: MONO/SCn_IN SCn_OUT1) D: MONO/SCn_IN SCn_OUT or unsel. O: MONO/SCn_IN I2S Output D: MONO/SCn_IN SCn_OUT O: I2S Input SCn_OUT1) D: MONO/SCn_IN unselected O: I2S Input SC1_OUT1) Crosstalk between Main and Aux Output pairs I2S Input DSP DACp1)
100 95 100 100
dB dB dB dB
90
dB
(unweighted 20 Hz...20 kHz) same signal source on left and right disturbing channel, effect on each observed output channel (unweighted 20 Hz...20 kHz) same signal source on left and right disturbing channel, effect on each observed output channel
XTALK
Crosstalk from Main or Aux Output to SCART Output and vice versa D = disturbing program O = observed program D: MONO/SCn_IN/DSP SCn_OUT O: I2S Input DACp1) D: MONO/SCn_IN/DSP SCn_OUT O: I2S Input DACp1) D: I2S Input DACp O: MONO/SCn_IN SCn_OUT1) D: I2S Input DACM O: I2S Input SCn_OUT1) 80 85 95 95 "p" means "M" or "A" dB dB dB dB
SCART output load resistance 10 k SCART output load resistance 30 k
1)
"n" means "1", "2", "3", or "4";
"s" means "L" or "R";
Micronas
65
MSP 44x8G
4.6.3.10. Sound Standard Dependent Characteristics
Symbol Parameter Pin Name Min. Typ. Max.
PRELIMINARY DATA SHEET
Unit
Test Conditions
NICAM Characteristics (MSP Standard Code = 8) dVNICAMOUT S/NNICAM Tolerance of Output Voltage of NICAM Baseband Signal S/N of NICAM Baseband Signal DACp_s SCn_OUT_s1) -1.5 72 +1.5 dB dB 2.12 kHz, Modulator input level = 0 dBref NICAM: -6 dB, 1 kHz, RMS unweighted 0 to 15 kHz, Vol = 9 dB NIC_Presc = 7Fh Output level 1 VRMS at DACp_s 2.12 kHz, Modulator input level = 0 dBref FM+NICAM, norm conditions Modulator input level = -12 dB dBref; RMS
THDNICAM BERNICAM fRNICAM XTALKNICAM SEPNICAM
Total Harmonic Distortion + Noise of NICAM Baseband Signal NICAM: Bit Error Rate NICAM Frequency Response, 20...15000 Hz NICAM Crosstalk Attenuation (Dual) NICAM Channel Separation (Stereo) -1.0 80 80
0.1 1 +1.0
% 10-7 dB dB dB
FM Characteristics (MSP Standard Code = 3) dVFMOUT S/NFM THDFM Tolerance of Output Voltage of FM Demodulated Signal S/N of FM Demodulated Signal Total Harmonic Distortion + Noise of FM Demodulated Signal DACp_s, SCn_OUT_s1) -1.5 73 0.1 +1.5 dB dB % 1 FM-carrier, 50 s, 1 kHz, 40 kHz deviation; RMS 1 FM-carrier 5.5 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS, unweighted 0 to 15 kHz (for S/N); full input range, FM-Prescale = 46 h, Vol = 0 dB Output Level 1 VRMS at DACp_s 1 FM-carrier 5.5 MHz, 50 s, Modulator input level = -14.6 dBref; RMS 2 FM-carriers 5.5/5.74 MHz, 50 s, 1 kHz, 40 kHz deviation; Bandpass 1 kHz 2 FM-carriers 5.5/5.74 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS
fRFM
FM Frequency Responses, 20...15000 Hz FM Crosstalk Attenuation (Dual)
-1.0
+1.0
dB
XTALKFM
80
dB
SEPFM
FM Channel Separation (Stereo)
50
dB
1) 2)
"n" means "1", "2", "3", or "4"; "s" means "L" or "R"; "p" means "M" or "A" EIM refers to 75-s Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation, when the DBX encoding process is replaced by a 75-s preemphasis network.
66
Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
AM Characteristics (MSP Standard Code = 9) S/NAM(1) S/NAM(2) THDAM fRAM S/N of AM Demodulated Signal measurement condition: RMS/Flat S/N of AM Demodulated Signal measurement condition: QP/CCIR Total Harmonic Distortion + Noise of AM Demodulated Signal AM Frequency Response 50 Hz... 12 kHz -2.5 DACp_s, SCn_OUT_s1) 55 45 0.6 +1.0 dB dB % dB SIF level: 0.1-0.8 Vpp AM-carrier 54% at 6.5 MHz Vol = 0 dB, FM/AM prescaler set for output = 0.5 VRMS at Main out; Standard Code = 09hex no video/chrominance components
BTSC Characteristics (MSP Standard Code = 20hex, 21hex) S/NBTSC S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal DACp_s, SCn_OUT_s1) 68 57 dB dB 1 kHz L or R or SAP, 100% modulation, 75 s deemphasis, RMS unweighted 0 to 15 kHz 1 kHz L or R or SAP, 100% 75 s EIM2), DBX NR, RMS unweighted 0 to 15 kHz L or R or SAP, 1%...66% EIM2), DBX NR
THDBTSC
THD+N of BTSC Stereo Signal THD+N of BTSC SAP Signal
0.1 0.5
% %
fRBTSC
Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSC SAP, 50 Hz...9 kHz
-0.5 -1.0 76 80
0.5 0.6
dB dB dB dB
XTALKBTSC
Stereo SAP SAP Stereo
1 kHz L or R or SAP, 100% modulation, 75 s deemphasis, Bandpass 1 kHz L or R 1%...66% EIM2), DBX NR 4.5 MHz carrier modulated with fh=15.743 kHz SIF level=100mVpp indication: STATUS Bit[6] standard BTSC stereo signal, sound carrier only
SepBTSC
Stereo Separation 50 Hz...10 kHz 50 Hz...12 kHz Pilot deviation threshold Stereo off on Stereo on off ANA_IN1+, ANA_IN2+
35 30
dB dB
FMThrPilot
3.2 1.2
3.5 1.5 15.843
kHz kHz kHz
fPilot
1) 2)
Pilot Frequency Range
ANA_IN1+ ANA_IN2+
15.563
"n" means "1", "2", "3", or "4"; "s" means "L" or "R"; "p" means "M" or "A" EIM refers to 75-s Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation, when the DBX encoding process is replaced by a 75-s preemphasis network.
Micronas
67
MSP 44x8G
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
BTSC Characteristics (MSP Standard Code = 20hex, 21hex) with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal components) S/NBTSC S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal DACp_s, SCn_OUT_s1) 64 55 dB dB 1 kHz L or R or SAP, 100% modulation, 75 s deemphasis, RMS unweighted 0 to 15 kHz 1 kHz L or R or SAP, 100% 75 s EIM2), DBX NR, RMS unweighted 0 to 15 kHz L or R or SAP, 1%...66% EIM2), DBX NR
THDBTSC
THD+N of BTSC Stereo Signal THD+N of BTSC SAP Signal
0.15 0.8
% %
fRBTSC
Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSCSAP, 50 Hz...9 kHz
-0.5 -1.0 75 75
0.5 0.6
dB dB dB dB
XTALKBTSC
Stereo SAP SAP Stereo
1 kHz L or R or SAP, 100% modulation, 75 s deemphasis, Bandpass 1 kHz L or R 1%...66% EIM2), DBX NR
SepBTSC
Stereo Separation 50 Hz...10 kHz 50 Hz...12 kHz
35 30
dB dB
EIA-J Characteristics (MSP Standard Code = 30hex) S/NEIAJ S/N of EIA-J Stereo Signal S/N of EIAJ Sub-Channel THDEIAJ THD+N of EIA-J Stereo Signal THD+N of EIA-J Sub-Channel fREIAJ Frequency Response of EIA-J Stereo, 50 Hz...12 kHz Frequency Response of EIA-J SubChannel, 50 Hz...12 kHz XTALKEIAJ Main SUB Sub Main SEPEIAJ Stereo Separation 50 Hz...5 kHz 50 Hz...10 kHz -0.5 -1.0 66 80 DACp_s, SCn_OUT_s1) 60 60 0.2 0.3 0.5 0.5 dB dB % % dB dB dB dB 1 kHz L or R, 100% modulation, 75 s deemphasis, Bandpass 1 kHz EIA-J Stereo Signal, L or R 100% modulation 100% modulation, 75 s deemphasis 1 kHz L or R, 100% modulation, 75 s deemphasis, RMS unweighted 0 to 15 kHz
35 28
dB dB
FM-Radio Characteristics (MSP Standard Code = 40hex) S/NUKW THDUKW fRUKW S/N of FM-Radio Stereo Signal THD+N of FM-Radio Stereo Signal Frequency Response of FM-Radio Stereo 50 Hz...15 kHz Stereo Separation 50 Hz...15 kHz Pilot Frequency Range ANA_IN1+ ANA_IN2+ -1.0 DACp_s, SCn_OUT_s1) 70 0.1 0.5 dB % dB 1 kHz L or R, 100% modulation, 75 s deemphasis, RMS unweighted 0 to 15 kHz L or R, 1%...100% modulation, 75 s deemphasis
SepUKW fPilot
1) 2)
45 18.844 19.125
dB kHz standard FM radio stereo signal
"n" means "1", "2", "3", or "4"; "s" means "L" or "R"; "p" means "M" or "A" EIM refers to 75-s Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation, when the DBX encoding process is replaced by a 75-s preemphasis network.
68
Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
5. Appendix A: Overview of TV-Sound Standards 5.1. NICAM 728
Table 5-1: Summary of NICAM 728 sound modulation parameters
Specification Carrier frequency of digital sound Transmission rate Type of modulation Spectrum shaping Roll-off factor 1.0 Carrier frequency of analog sound component Power ratio between vision carrier and analog sound carrier Power ratio between analog and modulated digital sound carrier 6.0 MHz FM mono 10 dB 0.4 5.5 MHz FM mono 13 dB I 6.552 MHz B/G 5.85 MHz L 5.85 MHz 728 kbit/s Differentially encoded quadrature phase shift keying (DQPSK) by means of Roll-off filters 0.4 6.5 MHz AM mono terrestrial 10 dB cable 16 dB 13 dB 0.4 6.5 MHz FM mono D/K 5.85 MHz
10 dB
7 dB
17 dB
11 dB
China/ Hungary 12 dB
Poland 7 dB
Table 5-2: Summary of NICAM 728 sound coding characteristics
Characteristics Audio sampling frequency Number of channels Initial resolution Companding characteristics Coding for compressed samples Preemphasis Audio overload level Values 32 kHz 2 14 bit/sample near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks 2's complement CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz) +12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)
Micronas
69
MSP 44x8G
5.2. A2-Systems
PRELIMINARY DATA SHEET
Table 5-3: Key parameters for A2 Systems of Standards B/G, D/K, and M
Characteristics TV-Sound Standard Carrier frequency in MHz Vision/sound power difference Sound bandwidth Preemphasis Frequency deviation (nom/max) Transmission Modes Mono transmission Stereo transmission Dual sound transmission Identification of Transmission Mode Pilot carrier frequency Max. deviation portion Type of modulation / modulation depth Modulation frequency 54.6875 kHz 55.0699 kHz (L+R)/2 language A mono (L+R)/2 R language B mono (L-R)/2 50 s 27/50 kHz 75 s 17/25 kHz B/G 5.5 Sound Carrier FM1 D/K 6.5 13 dB 40 Hz to 15 kHz 50 s 27/50 kHz 75 s 15/25 kHz M 4.5 B/G 5.7421875 Sound Carrier FM2 D/K 6.2578125 6.7421875 20 dB M 4.724212
2.5 kHz
AM / 50% mono: unmodulated stereo: 117.5 Hz dual: 274.1 Hz 149.9 Hz 276.0 Hz
70
Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
5.3. BTSC-Sound System
Table 5-4: Key parameters for BTSC-Sound Systems
Aural Carrier (L+R) Carrier frequency (fh = 15.734 kHz) Sound bandwidth in kHz Preemphasis Max. deviation to Aural Carrier Max. Freq. Deviation of Subcarrier Modulation Type
1)
BTSC-MPX-Components Pilot fh (L-R) 2 fh 0.05 - 15 DBX 5 kHz 50 kHz1) SAP 5 fh 0.05 - 12 DBX 15 kHz 10 kHz FM Prof. Ch. 6.5 fh 0.05 - 3.4 150 s 3 kHz 3 kHz FM
4.5 MHz
Baseband 0.05 - 15 75 s
73 kHz (total)
25 kHz1)
AM
Sum does not exceed 50 kHz due to interleaving effects
5.4. Japanese FM Stereo System (EIA-J)
Table 5-5: Key parameters for Japanese FM-Stereo Sound System EIA-J
Aural Carrier FM Carrier frequency (fh = 15.734 kHz) Sound bandwidth Preemphasis Max. deviation portion to Aural Carrier Max. Freq. Deviation of Subcarrier Modulation Type Transmitter-sided delay Mono transmission Stereo transmission Bilingual transmission 20 s L+R L+R Language A 47 kHz 4.5 MHz EIA-J-MPX-Components (L+R) Baseband 0.05 - 15 kHz 75 s 25 kHz (L-R) 2 fh 0.05 - 15 kHz 75 s 20 kHz 10 kHz FM 0 s - L-R Language B Identification 3.5 fh - none 2 kHz 60% AM 0 s unmodulated 982.5 Hz 922.5 Hz
Micronas
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MSP 44x8G
5.5. FM Satellite Sound
PRELIMINARY DATA SHEET
Table 5-6: Key parameters for FM Satellite Sound
Carrier Frequency 6.5 MHz 7.02/7.20 MHz 7.38/7.56 MHz 7.74/7.92 MHz Maximum FM Deviation 85 kHz 50 kHz 50 kHz 50 kHz Sound Mode Mono Mono/Stereo/Bilingual Mono/Stereo/Bilingual Mono/Stereo/Bilingual Bandwidth 15 kHz 15 kHz 15 kHz 15 kHz Deemphasis 50 s adaptive adaptive adaptive
5.6. FM-Stereo Radio
Table 5-7: Key parameters for FM-Stereo Radio Systems
Aural Carrier (L+R) Carrier frequency (fp = 19 kHz) Sound bandwidth in kHz Preemphasis: - USA - Europe Max. deviation to Aural Carrier
1)
FM-Radio-MPX-Components Pilot fp (L-R) 2 fp 0.05 - 15 75 s 50 s 10% 90%1) 5% RDS/ARI 3 fp
10.7 MHz
Baseband 0.05 - 15 75 s 50 s
75 kHz (100%)
90%1)
Sum does not exceed 90% due to interleaving effects
72
Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
6.1. Demodulator Write and Read Registers for Manual Mode In case of Automatic Sound Select (MODUS[0]=1), any modifications of all DCO registers listed in Table 6-1 are ignored.
6. Appendix B: Manual Mode To adapt the modes of the STANDARD SELECT register to individual requirements, the MSP 44x8G offers a Manual Mode, which provides sophisticated programming of the MSP 44x8G. The Manual Mode can be used only in those cases, where user specific requirements concerning detection, identification, or carrier positioning have to be met. After the setting of the STANDARD SELECT register, the MSP 44x8G is set up for optimal behavior. Therefore, it is not recommended to use the Manual mode.
Table 6-1: Demodulator Write Registers; Subaddress: 10hex; these registers are not readable!
Demodulator Write Registers AUTO_FM/AM Address (hex) 00 21 MSPVersion 4418, 44581) Description 1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of Automatic Switching between NICAM and FM/AM in case of bad NICAM reception 2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic Switching between NICAM and FM/AM in case of bad NICAM reception A2_Threshold CM_Threshold DCO1_LO DCO1_HI DCO2_LO DCO2_HI 00 22 00 24 00 93 00 9B 00 A3 00 AB A2 Stereo Identification Threshold Carrier-Mute Threshold Note: Modifications are ignored for Automatic Sound Select = on (MODUS[0]=1) Increment channel 1 Low Part Increment channel 1 High Part Increment channel 2 Low Part Increment channel 2 High Part
1)
Reset Mode 00 00hex
Page 74
00 19hex 00 2Ahex 00 00hex 77
not in BTSC, EIA-J, and FM-Radio mode
Table 6-2: Demodulator Read Registers; Subaddress: 11hex; these registers are not writable!
Demodulator Read Registers C_AD_BITS ADD_BITS CIB_BITS ERROR_RATE Address (hex) 00 23 00 38 00 3E 00 57 MSPVersion 4410, 4450 Description NICAM-Sync bit, NICAM-C-Bits, and bit[2:0] of additional data bits NICAM: bit[10:3] of additional data bits NICAM: CIB1 and CIB2 control bits NICAM error rate, updated with 182 ms Page 78 78 78 78
Micronas
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MSP 44x8G
6.2. DSP Write and Read Registers for Manual Mode
PRELIMINARY DATA SHEET
Table 6-3: DSP-Write Registers; Subaddress: 12hex, all registers are readable as well
Write Register Additional Channel Matrix Modes Address (hex) 00 08 00 09 00 0A 00 41 00 0B 00 0C 00 0F Bits [7:0] Operational Modes and Adjustable Range [SUM/DIFF, AB_XCHANGE, PHASE_CHANGE_B, PHASE_CHANGE_A, A_ONLY, B_ONLY] Reset Mode 00hex Page 79
FM Fixed Deemphasis FM Adaptive Deemphasis Identification Mode
[15:8] [7:0]
[OFF, 50 s, 75 s] [OFF, WP1] [B/G, M]
OFF OFF B/G
79 79 79
00 15
[7:0]
Table 6-4: DSP Read Registers; Subaddress: 13hex, all registers are not writable
Additional Read Registers Stereo detection register for A2 Stereo Systems DC level readout FM1/Ch2-L DC level readout FM2/Ch1-R Address (hex) 00 18 00 1B 00 1C Bits [15:8] [15:0] [15:0] Output Range [80hex ... 7Fhex] [8000hex ... 7FFFhex] [8000hex ... 7FFFhex] 8 bit two's complement 16 bit two's complement 16 bit two's complement Page 80 80 80
6.3. Manual Mode: Description of Demodulator Write Registers 6.3.1. Automatic Switching between NICAM and Analog Sound In case of bad NICAM reception or loss of the NICAM-carrier, the MSP 44x8G offers an Automatic Switching (fall back) to the analog sound (FM/AMMono), without the necessity of the controller reading and evaluating any parameters. If a proper NICAM signal returns, switching back to this source is performed automatically as well. The feature evaluates the NICAM ERROR_RATE and switches, if necessary, all output channels which are assigned to the NICAM source, to the analog source, and vice versa. An appropriate hysteresis algorithm avoids oscillating effects (see Fig. 6-1). STATUS[9] and C_AD_BITS[11] (Addr: 0023hex) provide information about the actual NICAM-FM/AM-status.
Selected Sound
NICAM
analog Sound
ERROR_RATE threshold/2 threshold
Fig. 6-1: Hysteresis for automatic switching
6.3.1.1. Function in Automatic Sound Select Mode The Automatic Sound Select feature (MODUS[0]=1) includes the procedure mentioned above. By default, the internal ERROR_RATE threshold is set to 700dec. i.e.: - NICAM analog sound if ERROR_RATE > 700 - analog sound NICAM if ERROR_RATE < 700/2
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PRELIMINARY DATA SHEET
MSP 44x8G
6.3.1.2. Function in Manual Mode If the manual mode (MODUS[0]=0) is required, the activation and configuration of the Automatic Switching feature has to be done as described in Table 6-5. Note, that the channel matrix of the corresponding output channels must be set according to the NICAM mode and need not to be changed in the FM/AM-fallback case. Example: Required threshold = 500: bits [10:1]=00 1111 1010
The ERROR_RATE value of 700 corresponds to a BER of approximately 5.46*10-3/s. Individual configuration of the threshold can be done using Table 6-5, whereby the bits [0] and [11] of AUTO_FM are ignored. It is recommended to use the internal setting used by the standard selection. The optimum NICAM sound can be assigned to the MSP output channels by selecting one of the "Stereo or A/B", "Stereo or A", or "Stereo or B" source channels.
Table 6-5: Coding of Automatic NICAM/Analog Sound Switching; Reset Status: Mode 0; Automatic Sound Select is on (MODUS[0] = 1)
Mode 1 Description Automatic Switching with internal threshold (Default, if Automatic Sound Select is on) Automatic Switching with external threshold (Customizing of Automatic Sound Select) AUTO_FM [11:0] Addr. = 00 21hex Bit[11] = ignored Bit[10:1] = 0 Bit[0] = ignored Bit[11] = ignored Bit[10:1] = 25...1000 = threshold/2 Bit[0] = ignored ERROR_RATEThreshold/dec 700 Source Select: Input at NICAM Path1) NICAM or FM/AM, depending on ERROR_RATE
2
set by customer; recommended range: 50...2000
1)
The NICAM path may be assigned to "Stereo or A/B", "Stereo or A", or "Stereo or B" source channels (see Table 2-2 on page 11).
Table 6-6: Coding of Automatic NICAM/Analog Sound Switching; Reset Status: Mode 0; Automatic Sound Select is off (MODUS[0] = 0)
Mode 0 Description Forced NICAM (Automatic Switching disabled) Automatic Switching with internal threshold (Default, if Automatic Sound Select is on) Automatic Switching with external threshold (Customizing of Automatic Sound Select) Forced Analog Mono (Automatic Switching disabled) AUTO_FM [11:0] Addr. = 00 21hex Bit[11] =0 Bit[10:1] = 0 Bit[0] =0 Bit[11] =0 Bit[10:1] = 0 Bit[0] =1 Bit[11] =0 Bit[10:1] = 25...1000 = threshold/2 Bit[0] =1 Bit[11] =1 Bit[10:1] = 0 Bit[0] =1 ERROR_RATEThreshold/dec none Source Select: Input at NICAM Path always NICAM; Mute in case of no NICAM available NICAM or FM/AM, depending on ERROR_RATE
1
700
2
set by customer; recommended range: 50...2000 none always FM/AM
3
Micronas
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MSP 44x8G
6.3.2. A2 Threshold The threshold between Stereo/Bilingual and Mono Identification for the A2 Standard has been made programmable according to the user's preferences. An internal hysteresis ensures robustness and stability. Table 6-7: Write Register on I2C Subaddress 10hex: A2 Threshold Register Address THRESHOLDS 00 22hex (write) A2 THRESHOLD Register Function
PRELIMINARY DATA SHEET
Name
A2_THRESH
Defines threshold of all A2 and EIA_J standards for Stereo and Bilingual detection bit[11:0] 7F0hex ... 190hex ... 0A0hex force Mono Identification default setting after reset minimum Threshold for stable detection
recommended range: 0Ahex...3Chex
6.3.3. Carrier-Mute Threshold The Carrier-Mute threshold has been made programmable according to the users preferences. An internal hysteresis ensures stable behavior. Table 6-8: Write Register on I2C Subaddress 10hex: Carrier-Mute Threshold Register Address THRESHOLDS 00 24hex (write) Carrier-Mute THRESHOLD Register Defines threshold for the carrier mute feature bit[6:0] 00hex ... 2Ahex ... FFhex Carrier-Mute always ON (both channels muted) default setting after reset Carrier-Mute always OFF (both channels forced on) CM_THRESH Function Name
recommended range: 14hex...50hex
76
Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
6.4. Manual Mode: Description of Demodulator Read Registers Note: This register should be used only in cases where software compatibility to the MSP 44x0D is required. Using the STANDARD SELECTION register together with the STATUS register provides a more economic way to program the MSP 44x8G and to retrieve information from the MSP. All registers except C_AD_BITs are 8 bits wide. They can be read out of the RAM of the MSP 44x8G. All transmissions take place in 16-bit words. The valid 8-bit data are the 8 LSBs of the received data word. If the Automatic Sound Select feature is not used, the NICAM or FM-identification parameters must be read and evaluated by the controller in order to enable appropriate switching of the channel select matrix of the baseband processing part. The FM-identification registers are described in Section 6.6.1. To handle the NICAM-sound and to observe the NICAM-quality, at least the registers C_AD_BITS and ERROR_RATE must be read and evaluated by the controller. Additional data bits and CIB bits, if supplied by the NICAM transmitter, can be obtained by reading the registers ADD_BITS and CIB_BITS.
6.3.4. DCO-Registers Note: The use of this register is not recommended. It should be used only in cases where non-standard carrier frequencies have to be processed. Please note, that the usage of user specific demodulation frequencies is not possible in combination with the Automatic Sound Select (MODUS[0]=1). When selecting a TV-sound standard by means of the STANDARD SELECT register, all frequency tuning is performed automatically. If manual setting of the tuning frequency is required, a set of 24-bit registers determining the mixing frequencies of the quadrature mixers can be written manually into the MSP. In Table 6-9, examples for DCO register programming are listed. It is necessary to separate these registers into two categories: low part and high part. The formula for the calculation of the INCR values for any chosen IF frequency is as follows: INCRdec = int (f / fs 224) with: int = integer function f = IF frequency in MHz fS = sampling frequency (18.432 MHz) Conversion of INCR into hex-format and separation of the 12-bit low and high parts lead to the required register values (DCO1_HI and _LO for MSP-Ch1, DCO2_HI and _LO for MSP-Ch2).
Table 6-9: DCO registers for the MSP 44x8G; reset status: DCO_HI/LO = "00 00"
DCO1_LO 00 93hex, DCO1_HI 00 9Bhex; DCO2_LO 00 A3hex, DCO2_HI 00 ABhex IF-Freq. [MHz] 4.5 5.04 5.5 5.58 5.7421875 6.0 6.2 6.5 6.552 7.02 7.38 DCO_HI [hex] 03 E8 04 60 04 C6 04 D8 04 FC 05 35 05 61 05 A4 05 B0 06 18 06 68 DCO_LO [hex] 00 00 00 00 03 8E 00 00 00 AA 05 55 0C 71 07 1C 00 00 00 00 00 00 5.76 5.85 5.94 6.6 6.65 6.8 7.2 7.56 05 00 05 14 05 28 05 BA 05 C5 05 E7 06 40 06 90 00 00 00 00 00 00 0A AA 0C 71 01 C7 00 00 00 00 IF-Freq. [MHz] DCO_HI [hex] DCO_LO [hex]
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MSP 44x8G
6.4.1. NICAM Mode Control/Additional Data Bits Register NICAM operation mode control bits and A[2:0] of the additional data bits. Format:
MSB
11 Auto _FM ... ... 7 A[2]
PRELIMINARY DATA SHEET
6.4.2. Additional Data Bits Register Contains the remaining 8 of the 11 additional data bits. The additional data bits are not yet defined by the NICAM 728 system. Format:
C_AD_BITS 00 23hex
6 A[1] 5 A[0] 4 C4 3 C3 2 C2 1 C1
LSB
0 S
MSB
7 A[10] 6 A[9] 5
ADD_BITS 00 38hex
4 A[7] 3 A[6] 2 A[5] 1 A[4]
LSB
0 A[3]
A[8]
Important: "S" = Bit[0] indicates correct NICAM-synchronization (S = 1). If S = 0, the MSP 4418/4458G has not yet synchronized correctly to frame and sequence, or has lost synchronization. The remaining read registers are therefore not valid. The MSP mutes the NICAM output automatically and tries to synchronize again as long as any NICAM standard is selected by the STANDARD SELECT register. The operation mode is coded by C4-C1 as shown in Table 6-10. Table 6-10: NICAM operation modes as defined by the EBU NICAM 728 specification
C4 0 0 0 0 1 1 1 C3 0 0 0 0 0 0 0 C2 0 0 1 1 0 0 1 C1 0 1 0 1 0 1 0 Operation Mode Stereo sound (NICAMA/B), independent mono sound (FM1) Two independent mono signals (NICAMA, FM1) Three independent mono channels (NICAMA, NICAMB, FM1) Data transmission only; no audio Stereo sound (NICAMA/B), FM1 carries same channel One mono signal (NICAMA). FM1 carries same channel as NICAMA Two independent mono channels (NICAMA, NICAMB). FM1 carries same channel as NICAMA Data transmission only; no audio Unimplemented sound coding option (not yet defined by EBU NICAM 728 specification)
6.4.3. CIB Bits Register CIB bits 1 and 2 (see NICAM 728 specifications). Format:
MSB
7 x 6 x 5 x
CIB_BITS 00 3Ehex
4 x 3 x 2 x 1 CIB1
LSB
0 CIB2
6.4.4. NICAM Error Rate Register
ERROR_RATE Error free maximum error rate 00 57hex 0000hex 07FFhex
Average error rate of the NICAM reception in a time interval of 182 ms, which should be close to 0. The initial and maximum value of ERROR_RATE is 2047. This value is also active if no NICAM-standard is selected. Since the value is achieved by filtering, a certain transition time (approx. 0.5 sec) is unavoidable. Acceptable audio may have error rates up to a value of 700dec. Individual evaluation of this value by the controller and an appropriate threshold may define the fallback mode from NICAM to FM/AM-Mono in case of poor NICAM reception. The bit error rate per second (BER) can be calculated by means of the following formula: BER = ERROR_RATE * 12.3*10-6 /s
1 x
0 1
1 x
1 x
AUTO_FM: monitor bit for the AUTO_FM Status: 0: NICAM source is NICAM 1: NICAM source is FM
Note: It is not necessary to read out and evaluate the C_AD_BITS. All evaluation is performed in the MSP and indicated in the STATUS register.
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Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
6.5.3. FM Adaptive Deemphasis
FM Adaptive Deemphasis WP1 L L L L L L 40hex 50hex 60hex 70hex 80hex 90hex OFF WP1 00 0Fhex 0000 0000 RESET 0011 1111 L 00hex 3Fhex
6.5. Manual Mode: Description of DSP Write Registers 6.5.1. Additional Channel Matrix Modes
Main Matrix Aux Matrix SCART1 Matrix SCART2 Matrix I2S Matrix Quasi-Peak Detector Matrix SUM/DIFF AB_XCHANGE PHASE_CHANGE_B PHASE_CHANGE_A A_ONLY B_ONLY 00 08hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000
Note: The Adaptive Deemphasis WP1 requires setting of fixed deemphasis to 75s.
6.5.4. NICAM Deemphasis A J17 Deemphasis is always applied to the NICAM signal. It is not switchable.
6.5.5. Identification Mode for A2 Stereo Systems
Identification Mode Standard B/G (German Stereo) Standard M (Korean Stereo) 00 15hex 0000 0000 RESET 0000 0001 0011 1111 L 00hex 01hex 3Fhex
This table shows additional modes for the channel matrix registers. The sum/difference mode can be used together with the quasi-peak detector to determine the sound material mode. If the difference signal on channel B (right) is near to zero, and the sum signal on channel A (left) is high, the incoming audio signal is mono. If there is a significant level on the difference signal, the incoming audio is stereo.
Reset of Ident-Filter
To shorten the response time of the identification algorithm after a program change between two FM-Stereo capable programs, the reset of the ident-filter can be applied. Sequence: 1. Program change
6.5.2. FM Fixed Deemphasis
FM Deemphasis 50 s 75 s OFF 00 0Fhex 0000 0000 RESET 0000 0001 0011 1111 H 00hex 01hex 3Fhex
2. Reset ident-filter 3. Set identification mode back to standard B/G or M 4. Read stereo detection register
Micronas
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MSP 44x8G
6.6. Manual Mode: Description of DSP Read Registers All readable registers are 16-bit wide. Transmissions via I2C bus have to take place in 16-bit words. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. These registers are not writable.
PRELIMINARY DATA SHEET
6.7. Demodulator Source Channels in Manual Mode 6.7.1. Terrestrial Sound Standards Table 6-11 shows the source channel assignment of the demodulated signals in case of manual mode for all terrestrial sound standards. See Table 2-2 for the assignment in the Automatic Sound Select mode. In manual mode for terrestrial sound standards, only two demodulator sources are defined.
6.6.1. Stereo Detection Register for A2 Stereo Systems
Stereo Detection Register Stereo Mode MONO STEREO BILINGUAL 00 18hex H
6.7.2. SAT Sound Standards Table 6-12 shows the source channel assignment of the demodulated signals for SAT sound standards.
Reading (two's complement) near zero positive value (ideal reception: 7Fhex) negative value (ideal reception: 80hex)
Note: It is not necessary to read out and evaluate the A2 identification level. All evaluation is performed in the MSP and indicated in the STATUS register.
6.6.2. DC Level Register
DC Level Readout FM1 (MSP-Ch2) DC Level Readout FM2 (MSP-Ch1) DC Level 00 1Bhex 00 1Chex H+L H+L
[8000hex ... 7FFFhex] values are 16 bit two's complement
The DC level register measures the DC component of the incoming FM signals (FM1 and FM2). This can be used for seek functions in satellite receivers and for IF FM frequencies fine tuning. If the DCO frequency is lower than the actuel carrier frequency, the resulting DC level will be positive, an dvia versa. In the audio signal the DC content is suppressed. The time constant , defining the transition time of the DC Level Register, is approximately 28 ms.
80
Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
Table 6-11: Manual Sound Select Mode for Terrestrial Sound Standards
Source Channels of Sound Select Block Broadcasted Sound Standard B/G-FM D/K-FM M-Korea M-Japan Selected MSP Standard Code 03 04, 05 02 30 Broadcasted Sound Mode MONO STEREO BILINGUAL, Languages A and B B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM
(with high deviation FM)
FM Matrix
FM/AM
(use 0 for channel select)
Stereo or A/B
(use 1 for channel select)
Sound A Mono German Stereo Korean Stereo No Matrix Sound A Mono
Mono Stereo Left = A Right = B analog Mono
Mono Stereo Left = A Right = B no sound with AUTO_FM: analog Mono
08 09 0A 0B 0C
NICAM not available or NICAM error rate too high MONO STEREO BILINGUAL, Languages A and B MONO
Sound A Mono Sound A Mono Sound A Mono Sound A Mono Korean Stereo Sound A Mono Korean Stereo Sound A Mono
analog Mono analog Mono analog Mono Mono Stereo Mono Stereo Mono
NICAM Mono NICAM Stereo Left = NICAM A Right = NICAM B Mono Stereo Mono Stereo Mono
20
STEREO MONO + SAP
BTSC
STEREO + SAP MONO 21 STEREO MONO + SAP STEREO + SAP
No Matrix Sound A Mono Korean Stereo
Left = Mono Right = SAP Mono Stereo
Left = Mono Right = SAP Mono Stereo
FM-Radio
40
MONO STEREO
Table 6-12: Manual Sound Select Modes for SAT-reception (FM Matrix is set automatically)
Source Channels of Sound Select Block for SAT-Modes Broadcasted Sound Standard Selected MSP Standard Code 6, 50hex FM SAT 51hex Broadcasted Sound Mode FM/AM
(source select: 0)
Stereo or A/B
(source select: 1)
Stereo or A
(source select: 3)
Stereo or B
(source select: 4)
MONO STEREO BILINGUAL
Mono Stereo Left = A (FM1) Right = B (FM2)
Mono Stereo Left = A (FM1) Right = B (FM2)
Mono Stereo A (FM1)
Mono Stereo B (FM2)
Micronas
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MSP 44x8G
7. Appendix C: Application Information 7.1. Exclusions of Audio Baseband Features In general, all functions can be switched independently. Two exceptions exist: 1. NICAM cannot be processed simultaneously with secondary channel (see Fig. 2-3 and Fig. 2-2 on page 10). 2. FM adaptive deemphasis cannot be processed simultaneously with FM-identification.
PRELIMINARY DATA SHEET
7.2. Phase Relationship of Analog Outputs The analog output signals: Main, Aux, and SCART2 all have the same phases. The SCART1 output has opposite phase. Using the I2S-outputs for other DSPs or D/A converters, care must be taken to adjust for the correct phase.
I2S_IN1/2/3
I2S_OUT1/2
Main Aux
Audio Baseband Processing
SCART1 SCART2 SCART3 SCART4 MONO SCART DSP Input Select
SCART1-Ch. SCART1
SCART2-Ch.
SCART2
MONO, SCART1...4
SCART Output Select
Fig. 7-1: Phase diagram of the MSP 44x8G
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Micronas
PRELIMINARY DATA SHEET
MSP 44x8G
7.3. Application Circuit
IF 2 IN
if ANA_IN2+ not used
Tuner 2
Signal GND IF 1 IN
10 F + 3.3 F 56 pF 56 pF 56 pF + 100 nF 100 nF 18.432 MHz
C s. section 4.6.2.
8 V(5 V)
100 pF
56 pF
Tuner 1
ANA_IN1+
+ 10 F + 10 F 1 k
Alternative circuit for ANA_IN1+ for more attenuation of video components:
VREFTOP 58
XTAL_IN 71
AGNDC 45
ANA_IN1+ 67
ANA_IN2+ 69
XTAL_OUT 72
ANA_IN- 68
CAPL_M 40
CAPL_A 38
1 F 330 nF 330 nF 330 nF AHVSS 330 nF 330 nF AHVSS 330 nF 330 nF AHVSS 330 nF 49 ASG 47 SC4_IN_L 48 SC4_IN_R 80 STANDBYQ DVSS 79 ADR_SEL DVSS 3 I2C_DA 2 I2C_CL 75 ADR_WS 10 ADR_CL 8 ADR_DA 5 I2S_WS 4 I2S_CL 6 I2S_DA_OUT 7 I2S_DA_IN1 17 I2S_DA_IN2/3 22 I2S_DA_IN3 20 I2S_WS_3 19 I2S_CL_3 21 RESETQ 39 AHVSUP TESTEN 70 AVSS 13 DVSUP 44 AHVSS 66 AVSUP 35 VREF1 26 VREF2 16 DVSS 62 AVSS AUD_CL_OUT 74 D_CTR_I/O_0 78 D_CTR_I/O_1 77 SC2_OUT_R 33 SC2_OUT_L 34 DACA_R 24 1 nF 60 MONO_IN 56 SC1_IN_L 57 SC1_IN_R 55 ASG 53 SC2_IN_L 54 SC2_IN_R 52 ASG 50 SC3_IN_L 51 SC3_IN_R DACA_L 25 1 nF 1 F 1 F DACM_R 27 1 nF DACM_L 28 1 nF 1 F
Main Channel
Aux Channel Aux Channel/ FM-Modulator
5V 5V
330 nF
MSP 44x8G
SC1_OUT_L 37 SC1_OUT_R 36
100 + 100 + 100 + 100 +
22 F 22 F 22 F 22 F
RESETQ (from Controller, see section 4.6.3.3.)
220 pF 470 pF 1.5 nF 10 F DVSS
470 pF 1.5 nF 10 F
470 pF 1.5 nF 10 F
AHVSS
AHVSS
5V
5V
8V (5 V)
AHVSS
AVSS
Note: Pin numbers refer
to the PQFP80 package.
Micronas
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MSP 44x8G
8. Data Sheet History 1. Preliminary data sheet: "MSP 44x8G Multistandard Sound Processor Family, Feb. 25, 2000, 6251-516-1PD. First release of the preliminary data sheet.
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com
Printed in Germany Order No. 6251-516-1PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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MSP 34xxG
Preliminary Data Sheet Supplement
Subject: Data Sheet Concerned: Supplement: Edition:
MSP 34xxG Version History All MSP 34xxG Data Sheets No. 2/ 6251-525-2PDS Oct. 11, 2000
Version Changes within the MSP 34xxG Family: For a detailed description of the below-mentioned items, see the corresponding data sheets. For quick reference, check the version history in the data sheet appendices.
MSP 34x0G MSP 34x1G MSP 34x2G MSP 34x5G MSP 34x7G technology power dissipation (typical) at 8 V operation 0.8 0.5 0.5 A4 B5 A4 B4 A1 B5 B6 A2 A1 B6 B6 0.5 B8 B8 0.45 B8 B8
MSP 34x0/x1/x5/x7 740 mW 640 mW 640 mW 640 mW 600 mW 690 mW MSP 34x2 x 8.4 V 8.4 V 8.7 V x x x x 8.7 V x x x x x x x x x x 8.7 V x x x x x x x x x x x x x
digital input specification change specification of max. analog high voltage (AHVSUP) programmable A2 and carrier mute thresholds new Standard Select Mode 0Dhex: D/K-NICAM together with HDEV3 FM mode additional preference "color" for 4.5 MHz carrier in Automatic Standard Detection improved AM-performance (better SNR and THD) new Standard Select Mode 07hex: D/K3 for Poland faster system D/K loop for stereo detection (standards 4, 5, 7, B with ASS = on) improved I2C hardware problem handling extended features in the CONTROL register (readout hardware / reset status) Micronas Dynamic Bass (MDB) Micronas Dynamic Bass (improved MDB) faster identification for all standards, major speedup of identification for EIA-J standard faster carrier mute J17 deemphasis MSP 34x0/x1/x2 MSP 34x0/x1/x2
Micronas
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